AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

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ID 683049
Date 12/19/2017
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design x
Reference Design Block Diagram Key Features Submodules in the Top-Level HDL Files Requirements Reference Design Walkthrough Procedures in the main.tcl System Console Script Document Revision History for AN 833: Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Requirements x
Hardware Requirements Software Requirements
Reference Design Walkthrough x
Hardware Set Up Running the Reference Design Viewing the Results Rebuilding Design
Running the Reference Design x
Compiling the Project to Include Signal Tap II File Setting Up the TI ADC12DJxx00 GUI Software and Board Configuring the FPGA Checking the Basic Operation Executing the .tcl Code and Initializing the JESD204B Links Checking the Deterministic Latency
Viewing the Results x
Link Up Test Results Short Transport Layer and Ramp Test Mode Test Results Deterministic Latency Test Results
Short Transport Layer and Ramp Test Mode Test Results x
Verifying Short Transport Test Patterns at Receiver Transport Layer Verifying Ramp Pattern at Output Data of DLL to the Input Receiver Transport Layer
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

Rebuilding Design

You need to regenerate the platform designer system if you want to modify the system, such as IP components settings and interfaces.

To regenerate the HDL files for the top level platform designer system, follow these steps:

  1. Open altera_jesd204_ed_qsys_RX.qsys.
  2. In the platform designer GUI, click Generate > Generate HDL.
    Note: If you want to modify the JESD204B IP cores, Transceiver PHY Reset Controller, and other component settings, right click on the altera_jesd204_subsystem_RX component and select Drill into Subsystem. After the modification, save the system. Go back to the top level platform designer system file and generate the HDL files.
  3. To rerun design in hardware, follow the steps in the Running the Reference Design section.
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