AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

ID 683049
Date 12/19/2017

Rebuilding Design

You need to regenerate the platform designer system if you want to modify the system, such as IP components settings and interfaces.

To regenerate the HDL files for the top level platform designer system, follow these steps:

  1. Open altera_jesd204_ed_qsys_RX.qsys.
  2. In the platform designer GUI, click Generate > Generate HDL.
    Note: If you want to modify the JESD204B IP cores, Transceiver PHY Reset Controller, and other component settings, right click on the altera_jesd204_subsystem_RX component and select Drill into Subsystem. After the modification, save the system. Go back to the top level platform designer system file and generate the HDL files.
  3. To rerun design in hardware, follow the steps in the Running the Reference Design section.