AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

ID 683049
Date 12/19/2017

Checking the Deterministic Latency

To check for deterministic latency, follow these steps:
  1. Restart the converter and reprogram the clocks and ADC.
  2. Restart and reconfigure the FPGA.
  3. Execute the .tcl code to initialize the JESD204B links.
  4. Read the RX Buffer Delay (RBD) count by typing the read_rx_status0 procedure in the Tcl Console and record the value. The RBD count is from the csr_rbd_count field in the rx_status0[10:3] register (at offset 0x80).
  5. Measure and record the number of link counts between the start of combined SYNC_N deassertion output from the two JESD204B IP cores to the first user data output, which is the assertion of the jesd204_rx_link_valid signal. Ensure the latency is constant for every converter and FPGA power cycle.
  6. Repeat step 1 to step 5 for a few times.

Example of the System Console output after executing the read_rx_status0 procedure:

% read_rx_status0
master_list_length = 1
RX Status0 (Link 0)= 0x00000009
RX Status0 (Link 1)= 0x00000009

RX Status0 = 0x00000009 indicates the following conditions:

  • bit[0]=1, JESD204B link is out of synchronization (SYNC_n deasserted).
  • bit[3]=1, csr_rbd_count = 1

For detailed description of the csr_rbd_count field of the rx_status0[10:3] register (at offset 0x80), refer to the Addressmap Information for 'altera_jesd204_rx_regmap'.