AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

ID 683049
Date 12/19/2017

Verifying Ramp Pattern at Output Data of DLL to the Input Receiver Transport Layer

You can run the ramp test mode after running the short transport pattern test. In this mode, the JESD04B link layers operate normally, but the transport layers are disabled. After the initial lane alignment sequence (ILAS), each lane transmits an identical octet stream that increments from 0x00 to 0xFF and repeats.

To verify the ramp pattern at output data of DLL to the input receiver transport layer, follow these steps:

  1. Change the command in line 7 of the ADC12DJxx00_JMODE1.cfg file to: 0x0205 0x04 // Set JTEST to 4 gives ramp test mode.
  2. Reprogram the clocks and ADC.
  3. Reconfigure the FPGA.
  4. Type the start_basic_test procedure in the System Console Tcl Console to execute the .tcl script to initialize the JESD204B links.
  5. In the Instance Manager, click rx_link > run Analysis.
  6. If you want to check the JESD204B link up process, set a trigger condition to the dev_sync_n signal. The signal tap waits for trigger condition to occur. The trigger condition should occur once you execute the start_basic_test procedure.
Figure 11. Octet Ramp Pattern Captured at the Output of DLL