AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

ID 683049
Date 12/19/2017

Link Up Test Results

Figure 8. Successful Link Up Indicated in the System ConsoleThis figure illustrates the expected output from the Tcl Console of the System Console if the link up is successful.

When the link up is successful, you should observe the following conditions:

  • USER_LED0USER_LED3 (D12–D15) illuminate
  • USER_LED4 (D16) turned off
Figure 9. On-board User LEDs
Table 2.  On-board User LEDs Indication
On-board User LED Signal Indication when LED Illuminates
LED D12 rx_frame_rst_n The transport layers and test pattern checkers are out of reset.
LED D13 rx_link_rst_n The IP cores, transport layers, and deterministic latency module are out of reset.
LED D14 alldev_lane_aligned All lanes are aligned for two JESD204B IP cores receiver.
LED D15 rx_dev_sync_n_out The receivers at link 0 and link 1 have successful received K28.5 characters.
LED D16 rx_link_error The interrupt is triggered at any of the JESD204B RX IP cores.