AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

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ID 683049
Date 12/19/2017
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design x
Reference Design Block Diagram Key Features Submodules in the Top-Level HDL Files Requirements Reference Design Walkthrough Procedures in the main.tcl System Console Script Document Revision History for AN 833: Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
Requirements x
Hardware Requirements Software Requirements
Reference Design Walkthrough x
Hardware Set Up Running the Reference Design Viewing the Results Rebuilding Design
Running the Reference Design x
Compiling the Project to Include Signal Tap II File Setting Up the TI ADC12DJxx00 GUI Software and Board Configuring the FPGA Checking the Basic Operation Executing the .tcl Code and Initializing the JESD204B Links Checking the Deterministic Latency
Viewing the Results x
Link Up Test Results Short Transport Layer and Ramp Test Mode Test Results Deterministic Latency Test Results
Short Transport Layer and Ramp Test Mode Test Results x
Verifying Short Transport Test Patterns at Receiver Transport Layer Verifying Ramp Pattern at Output Data of DLL to the Input Receiver Transport Layer
Intel® Stratix® 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

Configuring the FPGA

To configure the FPGA, follow these steps:
  1. Before configuring the FPGA, ensure the following:
    1. The Intel® FPGA Download Cable II driver is installed on the host computer.
    2. The Intel® Stratix® 10 Transceiver Signal Integrity Development Kit is powered on.
    3. No other running application is using the JTAG chain.
  2. In the Intel® Quartus® Prime Programmer, select Hardware Setup > Stratix 10H SI Dev Kit[USB-1].
  3. Click Auto Detect to display the devices in the JTAG chain. Select device 1SG280HU2S1.
  4. Right click and select Change File. Choose the appropriate SRAM Object File (.sof) from the <project directory>/output_files directory. Click Open.
  5. Turn on Program/Configure for the .sof file.
  6. Click Start to program the image into the FPGA.
Figure 5.  Intel® Quartus® Prime Programmer
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