AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

ID 683049
Date 12/19/2017

Submodules in the Top-Level HDL Files

The top-level HDL files of this reference design instantiate the following submodules:

  • Top level Platform Designer system
    • JESD204B subsystem includes reset sequencer, two ×8-lane RX JESD204B IP cores, transceiver PHY reset controller, and Avalon® Memory-Mapped (Avalon-MM) pipeline bridge.
    • JTAG-to- Avalon® master bridge for the System Console.
    • Link clock and frame clock generated by the core PLL.
    • Serial peripheral interface (SPI) master—Optional component in this design. You can use this component in your custom design if needed.
  • RX transport layers for link 0 and link 1
  • Test pattern checker
    Note: This test pattern checker is an optional module for this design example and is not suitable to test the ramp pattern transmitted from the ADC12DJ3200 device.
  • Deterministic latency measurement
  • Frequency checker