AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

ID 683049
Date 12/19/2017

Deterministic Latency Test Results

A system is deterministic if latency is repeatable from power-up cycle to power-up cycle. In this design, the JESD204B IP cores are configured as subclass 1 mode to support deterministic latency. The TI ADC12DJ3200 EVM uses AC coupling for SYSREF+/- , thus the periodic SYSREF signal is required to achieve deterministic latency. The SYSREF period from LMK04828 is configured to run at a frequency equals to the Local Multi-Frame Clock (LMFC) frequency before the SYSREF signal is supplied to the ADC and FPGA. The SYSREF pulse restarts the LMFC counter on the JESD204B IP cores and converter device, and realigns the LMFC counter to the LMFC boundary.

To ensure the deterministic latency in the reference design, follow these steps:

  1. Check the FPGA SYSREF single detection.
    For detailed description of the registers in the JESD204B RX IP core, refer to the Addressmap Information for 'altera_jesd204_rx_regmap'.
    Passing criteria: The value of csr_sysref_singledet and csr_sysref_lmfc_err should be zero.
    Figure 12.  csr_sysref_singledet and csr_sysref_lmfc_err Observed from the .tcl Console
  2. Check the SYSREF captured.
    Passing criteria: If the SYSREF is sampled correctly, the LMFC counter should be reset. Thus, the RBD_count value should only drift within 1–2 link clocks from one power cycle to another power cycle. In this test, the RBD_count is consistently 1 across 5 power cycle tests. It means the /R/ character is consistently received at 1 LMFC count before the next LMFC boundary for 5 power cycle tests.
    Figure 13. Early RBD Release Opportunity for Latest Arrival Lane Within One LMFC
  3. Check the latency from the start of combined SYNC_N deassertion output from the two JESD204B IP cores to the first user data output.
    Passing criteria: You should observe consistent latency from the start of combined SYNC_n deassertion to the assertion of the jesd204_rx_link_valid signal. In this design test, you should consistently observe 67 link cycles clock from one power cycle to another.
    Figure 14. Measured Latency from the Start of Combined SYNC_n to the First User Data Output
  4. Ensure the data latency is fixed during user data phase.
    Passing criteria: The ramp pattern should be in perfect shape with no distortion.
    Figure 15. Ramp Pattern in Perfect Shape