AN 833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

ID 683049
Date 12/19/2017

Running the Reference Design

To run the reference design, follow these steps:

  1. Compile the project to include Signal Tap II file.
  2. Set up the TI ADC12DJxx00 GUI software and board.
  3. Configure the FPGA.
  4. Check the basic operation.
  5. Execute the Tcl Script File (.tcl) code and initialize the JESD204B links.
  6. Check for deterministic latency.