PCI Express* IP Support Center
The PCI Express (PCIe*) IP support center provides information about how to select, design, and implement PCIe links. There are also guidelines on how to bring up your system and debug the PCIe links. This page is organized into categories that align with a PCIe system design flow from start to finish.
Get support resources for Intel Agilex® 7, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 devices from the pages below. For other devices, search from the following links: FPGA Documentation Index, Training Courses, Videos, Design Examples, Knowledge Base.
1. Device Selection
Intel® FPGA Device Family
Refer to the tables on page Intel® FPGA IP for PCIe* for Device Support for Number of Hardened PCI Express IP Blocks and Device Configurations and Features Support to understand the PCIe support for Intel FPGAs.
You can compare the devices in the tables and select the right device for your PCIe system implementation.
2. User Guides and Reference Designs
User Guides
The PCIe IP solutions encompass Intel’s technology-leading PCIe hardened protocol stack that includes the transaction and data link layers; and hardened physical layer, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCIe IP also includes optional blocks, such as direct memory access (DMA) engines and single root I/O virtualization (SR-IOV). For more information, refer to the following user guides:
IP User Guides
Intel Agilex® 7 Devices
F-Tile IP User Guides
R-Tile IP User Guides
P-Tile IP User Guides
- Intel® FPGA P-Tile Avalon Streaming IP for PCI Express User Guide
- Intel FPGA P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCI Express User Guide
- Multi Channel DMA for PCI Express IP User Guide
Intel Stratix 10 Devices
P-Tile User Guides
- Intel FPGA P-Tile Avalon-ST Hard IP for PCI Express User Guide
- Intel FPGA P-Tile Avalon Memory Mapped IP for PCI Express User Guide
- Multi Channel DMA for PCI Express IP User Guide
H-Tile/L-Tile User Guides
- Multi Channel DMA for PCI Express IP User Guide
- Avalon Memory Mapped (Avalon-MM) Intel Stratix 10 Hard IP+ for PCI Express Solutions User Guide
- Intel Stratix 10 H-Tile/L-Tile Avalon Memory Mapped (AvalonMM) Hard IP for PCI Express User Guide
- Intel Stratix 10 Avalon Streaming (Avalon-ST) and Single Root I/O Virtualization (SR-IOV) Interface for PCI Express Solutions User Guide
- Intel Stratix 10 Configuration via Protocol (CvP) Implementation User Guide
Intel Arria 10 and Intel Cyclone 10 Devices
User Guides
- Intel Arria 10 and Intel Cyclone 10 GX Avalon Memory Mapped (Avalon-MM) Interface for PCI Express User Guide
- Intel Arria 10 or Intel Cyclone 10 GX Avalon Memory Mapped (Avalon-MM) DMA Interface for PCI Express Solutions User Guide
- Intel Arria 10 and Intel Cyclone 10 GX Avalon-ST Interface for PCI Express User Guide
- Intel Arria 10 Avalon Streaming (Avalon-ST) Interface with SR-IOV PCIe Solutions User Guide
- Intel® Quartus® Prime Pro Edition User Guide Partial Reconfiguration
- Intel Arria 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide
Design Example User Guides
Intel Agilex® 7 Devices
F-Tile Design Example User Guides
R-Tile Design Example User Guides
P-Tile Design Example User Guides
- Intel FPGA P-Tile Avalon Streaming (Avalon-ST) IP for PCI Express Design Example User Guide
- Intel FPGA P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCI Express Design Example
- Multi Channel DMA for PCI Express IP Design Example User Guide
Intel Stratix 10 Devices
P-Tile Design Example User Guides
- Intel FPGA P-Tile Avalon Streaming (Avalon-ST) IP for PCI Express Design Example User Guide
- Intel FPGA P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCI Express Design Example
- Multi Channel DMA for PCI Express IP Design Example User Guide
L/H-Tile Design Example User Guides
- Multi Channel DMA for PCI Express IP Design Example User Guide
- Intel Stratix 10 Avalon Streaming (Avalon-ST) IP for PCIe Design Example User Guide
- Intel Stratix 10 Avalon -MM Hard IP for PCIe Design Example User Guide
Intel Arria 10 and Intel Cyclone 10 Devices
User Guides
- Intel Arria 10 and Intel Cyclone 10 Avalon-ST Hard IP for PCIe Design Example User Guide
- Intel Arria 10 and Intel Cyclone 10 Avalon-MM Interface for PCIe Design Example User Guide
IP Release Notes
Intel Agilex® 7 Devices
Intel Stratix 10 Devices
- L/H-Tile Hard IP for PCI Express IP Core Release Notes
- P-Tile IP for PCI Express IP Core Release Notes
- Multi Channel DMA for PCI Express IP Release Notes
Intel Arria 10 and Intel Cyclone 10 Devices
PHY Interface for PCI Express (PIPE) Using the Intel Transceiver Native PHY IP Core
You can also implement just the physical layer of PCIe using the Transceiver Native PHY IP core and stitch it together with the remaining protocol layers implemented as soft logic in the FPGA fabric. This soft logic can be your own design or a third-party IP.
Find out more about the Transceiver Native PHY IP core in the PIPE chapter of the following user guides:
Intel Stratix 10 Devices
Intel Arria 10 Devices
Intel Cyclone 10 Devices
Reference Designs
Intel Stratix 10 Devices
- Gen3x16 Avalon-MM DMA with Internal Memory Reference Design (AN 881)
- Gen3x16 Avalon-MM DMA with External Memory (DDR4) Reference Design (AN 881)
- Gen3x16 Avalon-MM DMA with HBM2 Reference Design (AN 881)
- Gen3x16 Using the Avery BFM for Simulation (AN 811)
- Gen3x8 Avalon-MM DMA with Internal Memory (Wiki)
- Gen3x8 Avalon -MM DMA with External DDR3/DDR4 Memory (AN 829)
- Gen3x8 Avalon-MM DMA for Legacy Quartus® Version (AN 690)
- Gen3x8 Partial Reconfiguration over PCI Express Reference Design (AN 819)
Intel Arria 10 Devices
- Gen3x8 Avalon-MM DMA with External DDR3 Memory (AN 708)
- Gen3x8 Avalon-MM DMA Reference Design with Internal Memory (AN 690)
- How to run Avalon-MM DMA Design Part1 (video)
- How to run Avalon-MM DMA Design Part2 (video)
- SoC Hardware Partial Reconfiguration
- Static Update Partial Reconfiguration Tutorial - Intel Arria 10 GX Device Only (AN 817)
- Hierarchical Partial Reconfiguration over PCIe (AN 813)
- Hierarchical Partial Reconfiguration Tutorial - Intel Arria 10 GX Device Only (AN 806)
- Partially Reconfiguring a Design - Intel Arria 10 GX Device Only (AN 797)
- Partial Reconfiguration over PCIe (AN 784)
- Upto Gen2x8 PCIe Root Port with MSI
Intel Cyclone 10 Devices
Intel Legacy Devices
3. IP Integration
Refer to the Getting Started section and Physical Layout of Hard IP section of your chosen IP core user guide. You can also refer to the following documents for details:
Intel Stratix 10 Devices
- How to Implement PCI Express (PIPE) in Intel Stratix 10 FPGA Transceivers section of the Intel Stratix L- and H-Tile Transceiver PHY User Guide
- AN 778: Intel Stratix 10 Transceiver Usage Application Note
Intel Arria 10 Devices
Intel Cyclone 10 Devices
Additional Videos
Title |
Description |
|---|---|
Learn how to configure your Intel Arria 10 device using the PCIe protocol. |
|
PCIe Avalon-MM Master DMA Reference Design in Intel Arria 10 Device (Part 1) |
Learn how to set up the PCIe Avalon Memory Mapped (Avalon-MM) DMA reference design hardware in Intel Arria 10 devices for both the Linux and Windows operating systems from this Part 1 video. |
PCIe Avalon-MM Master DMA Reference Design in Intel Arria 10 Device (Part 2) |
Learn how to set up the PCIe Avalon Memory Mapped Master DMA reference design hardware in Intel Arria 10 devices for both the Linux and Windows operating systems from this Part 2 video. |
5. Debug
Intellectual Property (IP) Core Release Notes
Intel Agilex® 7 Devices
Intel Stratix 10 Devices
- Intel Stratix 10 Multi Channel DMA for PCI Express IP Release Notes
- L/H-Tile Hard IP for PCI Express IP Core Release Notes
- P-Tile IP for PCI Express IP Core Release Notes
Intel Arria 10 and Intel Cyclone 10 Devices
Fault Tree Analysis Guides
FPGA Resource Placement Guidelines
6. Additional Resources
Migrating to Intel Stratix 10 Devices
PCIe-SIG Integrators List
Explore Other Developer Centers
For other design guidelines, visit the following Developer Centers:
- Board Developer Center - Contains detailed guidelines and considerations for high-speed PCB designs with Intel® FPGAs and SoC FPGAs.
- Embedded Software Developer Center - Contains guidance on how to design in an embedded environment with SoC FPGAs.
- FPGA Developer Center - Contains resources to complete your Intel® FPGA design.