This document covers a reference design using the PCI Express* Avalon® Memory-Mapped ( Avalon® -MM) Direct Memory Access (DMA) with Memory IP Interfaces. This reference design demonstrates the performance of the Avalon® -MM Intel® Stratix® 10 Hard IP+ for PCI Express* , a high-performance DMA controller with two types of memory solutions: external (DDR4) and HBM2 memories.
The reference design includes a Linux* software driver to set up the DMA transfers with high-throughput data movers for DMA support. The Read Data Mover moves data from the system memory to the external or HBM2 memory in Avalon® -MM space . The Write Data Mover moves data from the external or HBM2 memory in the application logic to the system memory in PCIe* space. This reference design allows you to evaluate the performance of the Avalon® -MM Intel® Stratix® 10 Hard IP+ for PCI Express* while using the Avalon-MM interface with high-performance DMA with different memory IPs.
|Reference Design||Hardware||Throughput with HBM2 (GB/s)||Throughput with DDR4 (GB/s)||Gate Counts||Design Link|
|Avalon® -MM Intel® Stratix® 10 MX Hard IP+ DMA with HBM2 and DDR4||Intel® Stratix® 10 MX FPGA Development Kit||14.42||14.07||14.82||14.06||
|PCI Express Gen3 x16 AVMM DMA with HBM2 and DDR4 Reference Design|
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