AN 881: PCI Express* Gen3 x16 Avalon® Memory Mapped (Avalon-MM) DMA with DDR4 SDRAM and HBM2 Memories Reference Design

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ID 683291
Date 4/19/2021
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Reference Design Description 3. Understanding PCI Express* throughput 4. Document Revision History for AN 881: PCI Express* Gen3 x16 Avalon® Memory Mapped (Avalon-MM) DMA with External and HBM2 Memories Reference Design
1. Introduction x
1.1. PCI Express Gen3 x16 Avalon-MM DMA with External and HBM2 Memory Hardware and Software Requirements 1.2. Avalon-MM Bridge with DMA Module Description 1.3. DMA Procedure Steps 1.4. Setting Up the Hardware 1.5. Installing the DMA Test Driver and Running the Linux DMA Software
2. Reference Design Description x
2.1. Project Hierarchy 2.2. Parameter Settings for PCI Express* Hard IP Variations 2.3. PCIe Avalon-MM DMA Reference Design with External and HBM2 Memories Platform Designer System 2.4. Intel Stratix 10 MX DMA Memory Throughput
3. Understanding PCI Express* throughput x
3.1. Throughput for Posted Writes 3.2. Throughput for Reads
3.1. Throughput for Posted Writes x
3.1.1. Specifying the Maximum Payload Size
3.2. Throughput for Reads x
3.2.1. Understanding Throughput Measurement
1. Introduction
2. Reference Design Description
3. Understanding PCI Express* throughput
4. Document Revision History for AN 881: PCI Express* Gen3 x16 Avalon® Memory Mapped (Avalon-MM) DMA with External and HBM2 Memories Reference Design

2.3. PCIe Avalon-MM DMA Reference Design with External and HBM2 Memories Platform Designer System

The following image shows the modules in the Platform Designer system for this reference design.

Figure 7.  Avalon® -MM Intel® Stratix® 10 Hard IP+ for PCI Express* with External and HBM2 Memories Platform Designer System
Table 12.  Address Mapping
Interface Base and End Addresses Bursting Avalon Master (BAM) BAR
Intel DMA Controller 0x0000_0000 - 0x0000_0fff BAR0
HBM2 Memory Controller 0x8000_0000 - 0x8fff_ffff BAR2
Intel DDR4 Controller 0x1_0000_0000 - 0x1_3fff_ffff BAR4
Table 13.  Platform Designer Port Descriptions
Port Function Description
RDDM Read Data Mover This interface transfers DMA data from the PCIe* system memory to the memory in Avalon® -MM address space.
WRDM Write Data Mover

This interface transfers DMA data from the memory in Avalon® -MM address space to the PCIe* system memory.

BAM Bursting Avalon® -MM Master This interface provides host access to the registers and memory in Avalon® -MM address space. The Bursting Avalon® -MM Master module converts PCIe* Memory Reads and Writes to Avalon® -MM Reads and Writes.
Intel DDR4 Controller DDR4 Controller This is a single-port DDR4 controller with 64 DQ width and 8 DQ per DQS group.
HBM2 Memory Controller HBM Controller This is a single channel with 2 pseudo channel HBM Controllers. The user interface to the HBM2 Controller uses the AXI4 protocol. Each Controller has one AXI4 interface per pseudo channel or 2 AXI4 interfaces per channel.
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