AN 881: PCI Express* Gen3 x16 Avalon® Memory Mapped (Avalon-MM) DMA with DDR4 SDRAM and HBM2 Memories Reference Design

ID 683291
Date 4/19/2021

2.2. Parameter Settings for PCI Express* Hard IP Variations

This reference design supports a 512-byte maximum payload size. The following tables list the values for all the parameters.

Table 2.  System Settings
Parameter Value
Number of lanes Intel® Stratix® 10 MX: 16
Lane rate Intel® Stratix® 10 Gen3: 8 Gbps
Hard IP Mode By default, the Hard IP mode is set to Gen3 x16, with a 512-bit interface to the Application Layer running at 250 MHz.
Table 3.  Base Address Register (BAR) Settings
Parameter Value BAR Size
BAR0 64-bit prefetchable memory DMA: 16 bits
BAR1 Disabled  
BAR2 64-bit prefetchable memory HBM2: 30 bits
BAR3 Disabled  
BAR4 64-bit prefetchable memory DDR4: 30 bits
BAR5 Disabled  
Table 4.  Device Identification Register Settings
Parameter Value
Vendor ID 0x00001172
Device ID 0x0000E003
Revision ID 0x00000001
Class Code 0x00000000
Subsystem Vendor ID 0x00000000
Subsystem Device ID 0x00000000
Table 5.  PCI Express/PCI* Capabilities
Parameter Value
Maximum payload size 512 bytes
Completion timeout range None
Implement completion timeout Disabled
Table 6.  Error Reporting Settings
Parameter Value
Advanced Error Reporting (AER) Enabled
ECRC checking Disabled
ECRC generation Disabled
Table 7.  Link Settings
Parameter Value
Link port number 1
Slot clock configuration Enabled
Table 8.  Message Signaled Interrupts (MSI) and MSI-X Settings
Parameter Value
Number of MSI messages requested 4
Implement MSI-X Disabled
Table size 0
Table offset 0x0000000000000000
Table BAR indicator 0
Pending bit array (PBA) offset 0x0000000000000000
PBA BAR indicator 0
Table 9.  Power Management
Parameter Value
Endpoint L0s acceptable latency Maximum of 64 ns
Endpoint L1 acceptable latency Maximum of 1 us
Table 10.  PCIe Address Space Setting
Parameter Value
Address width of accessible PCIe memory space 40
Table 11.  DDR4 Memory
Parameter Value
Memory format UDIM