AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
Document Table of Contents

1. Transceiver Layout

Note: This application note applies to Intel® Stratix® 10 L-tile and H-tile production devices only.
Intel® Stratix® 10 devices support a transceiver tile architecture. A tile consists of 24 transceiver channels and associated phase locked loops (PLLs), reference clock buffers, and Hard IPs.

The range of capabilities in each tile type offers a customized solution suited to the various transceiver applications. The next section describes the L-tile in greater detail. An Intel® Stratix® 10 device contains one or more tiles on the left and right side of the device. The types of tiles do not have to be homogeneous.

Refer to the table "Transceiver Tile Variants—Comparison of Transceiver Capabilities" in the Overview chapter of the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide for additional information.

Figure 1. Transceiver Tile LayoutExample Intel® Stratix® 10 GX/SX device with an H-tile on the left side of the device.