AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
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3.1.3. Non-PCIe and PCIe Hard IP Channel Placement in L-Tile and H-Tile

For OTN or SDI channels that share a tile with active PCI Express interfaces with PCIe Hard IP enabled that are Gen2 or Gen3 capable and configured with more than four lanes (Gen2/3 x8, x16), the maximum data rate is less than 9 Gbps.

Running the OTN or SDI channels within the same tile at data rates faster than 9 Gbps may result in bit errors at the remote OTN or SDI device during PCI Express rate change events (PCIe link training both up and down, during link down and start of link training).

Avoid placing OTN or SDI channels above 9 Gbps in the same tile with PCI Express Hard IP interfaces that are Gen 2 or Gen 3 capable and configured with x8 or x16 lanes, or bring up the PCI Express channels first, followed by the OTN or SDI channels. Transceiver channels that share a tile with active PCI Express interfaces that are only Gen1 capable are not impacted.

Figure 40. Channel Placement for OTN or SDI channel > 9 Gbps and PCIe PIPE Channels in H-Tile