AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
Document Table of Contents ATX PLL Usage Model When Driving GXT Channels

  • If ATX PLL IP is configured as the “Main ATX PLL” (Local ATX PLL output) the ATX PLL Master Clock Generation Block (MCGB) cannot be used.
  • If ATX PLL IP is configured as an “Adjacent ATX PLL” (selecting input from ATX PLL below/above), the MCGB in the 3-pack cannot be used.
    • In the same 3-pack as a Main ATX PLL or Adjacent ATX PLL, the fPLL can be configured to drive the x1 clock lines.
Figure 31. Restrictions for ATX PLL GX and MCGB

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