AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
Document Table of Contents

1.1.1. PLLs

Each Intel® Stratix® 10 L-tile/H-tile transceiver bank includes the following TX Phase Locked Loops (PLLs):

  • Two Advanced Transmit (ATX) PLLs
  • Two Fractional PLLs (fPLL)
  • Two Clock Multiplier Unit (CMU) PLLs (Located in channel 1 and channel 4 of each bank)
Table 1.  Transmitter PLLs in Stratix 10 L-Tile/H-Tile Devices
PLL Type Characteristics
  • Best jitter performance
  • LC tank based voltage controlled oscillator (VCO)
  • Supports fractional synthesis mode (in cascade mode only)
  • Used for both bonded and non-bonded channel configurations
Fractional PLL (fPLL)
  • Ring oscillator based VCO
  • Supports fractional synthesis mode
  • Used for both bonded and non-bonded channel configurations
Clock Multiplier Unit (CMU) PLL or Channel PLL 1
  • Ring oscillator based VCO
  • Used as an additional clock source for non-bonded applications

The total number of TX PLLs per tile is:

  • Eight ATX PLLs (2 ATX PLLs per bank * 4 banks per tile)
  • Eight fPLLs (2 fPLLs per bank * 4 banks per tile)
  • Eight CMU PLLs (2 CMU PLLs per bank * 4 banks per tile)
Figure 2. Stratix 10 PLLs and Clock Networks in Two Banks of Intel® Stratix® 10 L-Tile/H-Tile The ATX PLL, fPLL and CMU PLLs can drive the x1 clock network to support non-bonded transceivers. The ATX PLL and fPLL can drive the x6 clock network to support bonded transceivers within the bank. The x6 clock network can drive the x24 clock network in adjacent banks, allowing ATX PLLs and fPLLs to support up to 24 bonded transceiver channels. The x1, x6, and x24 clock networks are described in the Transceiver Clock Network section.
Note: For further details on CGB, refer to "PLL and Clock Networks" chapter in Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide.
1 The CMU PLL or Channel PLL of channel 1 and channel 4 can be used as a transmitter PLL or as a clock data recovery (CDR) block. The channel PLL of all other channels (0, 2, 3, and 5) can only be used as a CDR.