AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
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2.4. Thermal Guidelines

Optimal thermal performance can be achieved by reducing the power density within the transceiver tile. Placing many high data rate channels next to each other results in high power density areas within a tile. Following a general guideline of minimizing power density results in a less complex, and cheaper cooling solution for the FPGA.

For best thermal performance you can minimize power density by picking transceiver channel locations early on. Follow these guidelines when placing your transceiver channels within a tile:

  • Spread out channels as much as possible
  • If all channels in a tile are used, intersperse low and high data rate channels
  • The middle of the tile has the best thermal performance, followed by the bottom and then the top of each tile when looking at the Pin Planner

The latest Intel® Stratix® 10 Power and Thermal Calculator (PTC) contains a Thermal worksheet to help you determine the impact of transceiver placement on your thermal solution requirements. Prior to finalizing your board design you should analyze your transceiver channel placement using the Intel® Stratix® 10 PTC to ensure it is thermally optimal.

Note: Contact your local FAE to have Intel run a thermal analysis of your board design after you have determined placement of all transceiver channels.