AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
Document Table of Contents

3.2.4. Non-PCIe and PCIe PIPE Channel Placement in L-Tile

For L-Tile ES1 and L-Tile Production devices, non-PCIe channels fulfilling the following channel placement rules may observe momentary bit errors (BER) when an active PCIe PIPE interface that are Gen2 or Gen3 capable and configured with more than 4 lanes (Gen2/3 x8, x16) goes through rate change event (PCIe link training both up and down, during link down and start of link training.

Avoid the following channel placements, or bring up the PCIe PIPE interface first, followed by the non-PCIe channels.
  • GX channels at data rates above 6.5 Gbps or GXT channels that share a bank with the PCI Express interface.
  • OTN or SDI channels at a data rate higher than 9 Gbps that share a tile with the PCI Express interface.
Transceiver channels that share a tile with active PCI Express interfaces that are only Gen1 capable are not impacted.
Figure 42. Channel Placement for GX channel > 6.5 Gbps or GXT channel and PCIe PIPE Channels in L-Tile
Figure 43. Channel Placement for OTN or SDI channel > 9 Gbps and PCIe PIPE channels in L-Tile