1.1.3. GXT Clock Network
Both the L-tile and H-tile contains the GXT clock network. The GXT clock network allows an ATX PLL to drive up to six transmitter channels—four in its bank and two in an adjacent bank. The GXT clock network is used for data rates above 17.4 Gbps. Refer to GXT Channels for specification details. See "Using the ATX PLL for GXT Channels" in the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide for an in-depth discussion of the GXT clock network and the ATX PLL usage of it.
Figure 9. Top ATX PLL GXT Network Reach (Right Side of Below Figure)If the ATX PLL is in the upper triplet, its drive span is all four GXT channels within its own bank and channels ch0 and ch1 of the bank above.
Figure 10. Bottom ATX PLL GXT Network Reach (Left Side of Below Figure)If the ATX PLL is in the bottom triplet, its drive span is all four GXT channels within its own bank and channels ch3 and ch4 from the bank below.
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