AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
Document Table of Contents

1.1.2. Transmitter Clock Network

The transmitter clock network routes the clock from the transmitter PLL to one or more transmitter channels. It provides two types of clocks to the transmitter channel:

  • High-Speed Serial Clock - high-speed clock for the serializer
  • Low-Speed Parallel Clock - low-speed clock for the serializer and the PCS

In a bonded channel configuration, both the serial clock and the parallel clock are routed from the transmitter PLL to the transmitter channels. In a non-bonded channel configuration, only the serial clock is routed to the transmitter channels, while the parallel clock is generated locally within each channel.

To support various bonded and non-bonded clocking configurations, three types of transmitter clock network lines are available:

  • x1 clock lines: Span a single bank within a tile and are used for non-bonded channel clocking only
  • x6 clock lines: Span a single bank within a tile and are used for bonded channel clocking
  • x24 clock lines: Span all banks within a tile and are used for both PMA bonded and PMA-PCS bonded transceiver channels.

All clock lines are contained within a single tile and cannot span across multiple tiles.

Figure 6. x1 Clock Lines
Figure 7. x6 Clock Lines
Figure 8. x24 Clock Lines
There are two x24 lines available per tile:
  • x24 Up: Routes clocks to transceiver banks located above the current bank
  • x24 Down: Routes clocks to transceiver banks located below the current bank

When using the x24 lines, the maximum channel span is two banks above and two banks below the master bank containing the instantiated TX PLL. If using the x24 clock lines across all four banks within the tile, the TX PLL must be instantiated in one of the middle banks to comply with the channel span requirements.

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