AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
Document Table of Contents

3.1.1. Channel Placement for PCIe Hard IP

The PCIe lane 0 is always mapped to ch0 of the transceiver tile. Channel 0 of the transceiver tile = Bank 0, Channel 0.

The PCIe x1, x2, x4 and x8 configurations always consume a total of eight transceiver channels.

CvP Support

Only the bottom left transceiver tile supports configuration via protocol (CvP).

Figure 34. Transceiver Channel Usage for PCIe x1, x2, x4, x8 and x16
Figure 35. Transceiver Channel Usage for PCIe x1, x2, x4 and x8 for Intel® Stratix® 10 GX 10M Devices

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