2.1.5. Reference Clock Guidelines for L-Tile and H-Tile
The transmitter PLL and the clock data recovery (CDR) block need an input reference clock source to generate the clocks required for transceiver operation. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations.
Intel® Stratix® 10 L-tile and H-tile transceiver PLLs have five possible input reference clock sources, depending on jitter requirements:
- Dedicated reference clock pins
- Receiver input pins
- Reference clock network
- PLL cascade output (fPLL only)
- Core clock network (fPLL only)
Intel recommends using the dedicated reference clock pins and the reference clock network for the best jitter performance.
- OTU2e, OTU2, OC-192 and 10G PON
- 6G and 12G SDI
The input reference clock is a differential signal. Intel recommends using the dedicated reference clock pin in the same bank as the transmitter PLL for optimal jitter performance. The input reference clock must be stable and free-running at device power-up for proper PLL operation and PLL calibration. If the reference clock is not available at device power-up, then PLL must be recalibrated when the reference clock is available.
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