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2.1.5. Reference Clock Guidelines for L-Tile and H-Tile
The transmitter PLL and the clock data recovery (CDR) block need an input reference clock source to generate the clocks required for transceiver operation. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations.
Intel® Stratix® 10 L-tile and H-tile transceiver PLLs have five possible input reference clock sources, depending on jitter requirements:
- Dedicated reference clock pins
- Receiver input pins
- Reference clock network
- PLL cascade output (fPLL only)
- Core clock network (fPLL only)
Note: Each core clock network reference clock pin cannot drive fPLLs located on multiple L/H-tiles.
Intel recommends using the dedicated reference clock pins and the reference clock network for the best jitter performance.
For the best jitter performance, Intel recommends placing the reference clock as close as possible to the transmitter PLL. The following protocols require the reference clock to be placed in same bank as the transmitter PLL:
- OTU2e, OTU2, OC-192 and 10G PON
- 6G and 12G SDI
Note: For optimum performance of GXT channel, the reference clock of transmitter PLL is recommended to be from a dedicated reference clock pin in the same triplet.
Figure 28. Input Reference Clock Sources
Note: In Intel® Stratix® 10 devices, the FPGA fabric core clock network can be used as an input reference source for fPLL only.
The input reference clock is a differential signal. Intel recommends using the dedicated reference clock pin in the same bank as the transmitter PLL for optimal jitter performance. The input reference clock must be stable and free-running at device power-up for proper PLL operation and PLL calibration. If the reference clock is not available at device power-up, then PLL must be recalibrated when the reference clock is available.
Figure 29. Dedicated Reference Clock Pins and Other Reference Clock SourcesIn Intel® Stratix® 10 L-tile and H-tile devices, dedicated reference clock pins and reference clock network can be used by the transmitter PLL (ATX PLL and fPLL).