The transceiver is calibrated at device power on. The OSC_CLK_1 signal is used for device configuration and by transceiver calibration logic. OSC_CLK_1 must be driven by a free running 25 MHz, 100 MHz, or 125 MHz clock source if the transceiver tiles are used. The internal FPGA oscillator cannot be used for transceiver calibration.
The clock source must be stable at FPGA device configuration and should continue to run during device operation.
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