AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
Document Table of Contents

3.2.2. PLL Placement for PIPE

When instantiating PIPE interfaces and PCIe Hard IP in the same transceiver tile, be aware of ATX-fPLL spacing rules. For more details refer to PLL Placement section.

TX PLL Guidelines When Using PCIe
  1. Intel® recommends that the remaining channels of the L-tile are to be driven by ATX PLL if 4 or more channels of PCIe are used at Gen2 or Gen3 speeds. Using ATX PLL to drive these channels helps achieve better performance. Intel® Quartus® Prime issues a critical warning if fPLL is used to drive the remaining channels.
    Table 14.  TX PLL Guidelines When Using PCIe
    PCIE CONFIG Recommended PLL selection for remaining channels
    PCIE GEN 1 (All lane widths) Any PLL
    PCIE GEN 2 (x4,x8,x16) ATX PLL 6
    PCIE GEN 3 (x4,x8,x16) ATX PLL6
  2. For details on PLL placement for PIPE, refer to the section "How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes" in Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide.
6 Intel® Quartus® Prime issues a critical warning if FPLL is used instead of ATX PLL.