AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
Public
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4. Document Revision History for AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

Document Version Changes
2022.06.24
  • Possible Combinations of GX and GXT Channels in H-Tile: Column name "Chip-to-chip" changed to "Chip-to-Chip & Chip-to-Module" for all tables in this section
  • Possible Combinations of GX and GXT Channels in H-Tile: Note added
  • Possible Combinations of GX and GXT Channels in L-Tile: Column name "Chip-to-chip" changed to "Chip-to-Chip & Chip-to-Module" for all tables in this section
2021.12.08 Made the following changes:
  • Added new topic Bonded Channel Placement with Data Rate Change in section Transceiver Channel Placement.
  • Added new figure Transceiver Channel Usage for PCIe x1, x2, x4 and x8 for Intel Stratix 10 GX10M Devices in section Channel Placement for PCIe Hard IP.
  • Added new topic Non-PCIe and PCIe Hard IP Channel Placement in L-Tile and H-Tile in section PCIe Hard IP.
  • Updated Channel Placement for PIPE topic in section PHY Interface for PCIe Express (PIPE).
  • Added new topic Non-PCIe and PCIe PIPE Channel Placement in H-Tile in section PHY Interface for PCIe Express (PIPE).
  • Added new topic Non-PCIe and PCIe PIPE Channel Placement in L-Tile in section PHY Interface for PCIe Express (PIPE).
2020.04.21 Made the following changes:
  • Changed ADME to NPDME.
  • Updated PCIe hard IP and PIPE spacing requirements for H-tile.
  • Updated to apply to Intel® Stratix® 10 L-tile/H-tile production devices only.
2018.07.13 Made the following changes:
  • Updated the "ATX PLL Block Diagram" figure to clearly show that cascaded input from an upstream PLL is not supported.
  • Added "These combinations are only applicable for banks GXB1D/H/L and GXB4D/H/L and GXB1F/J/N and GXB4F/J/N." note to Possible Combinations of GX and GXT Channels in L-Tile.
2017.11.06 Made the following changes:
  • Updated the "Channel Types" table to include L-Tile channels
  • Updated the "ATX PLL Spacing Requirements" and "ATX PLL-fPLL Spacing Requirements" table
  • Updated the "Thermal Guidelines" section
  • Made the following updates in the "Mix and Match GX Channels Design Example" diagram:
    • Changed PCIe Gen 1/2/3 x8 to PCIe HIP Gen 1/2/3x8
    • Changed PCIe Gen 1/2 , 2.5 GHz to PCIe HIP Gen 1/2 , 2.5 GHz
    • Changed PCIe Gen 3, 4 GHz to PCIe HIP Gen 3, 4 GHz
  • Updated the description for "TX PLL Restrictions when Using PCIe x16" topic
  • Updated the description for "PCIe Hard IP Placement" topic
  • Restrictions stated when one or more channels in a bank are used for PCIe/PIPE Gen3
  • Updated steps in "How to Place Channels for PIPE Configurations" topic
  • Changed value of Logical PCS Master Channel # from 1 to 0 in "Logical PCS Master Channel for PIPE Configuration" table
  • Added a note "Each core clock network reference clock pin cannot drive fPLLs located on multiple L/H-Tiles"
  • Added a new diagram "x4 Configuration" in "Bonded GX Channels" topic to explain the ascending order of the channel placement
2017.01.13 Made the following change:
  • Added a new section: ATX PLL GXT Channels Placement
2016.12.19 Made the following changes:
  • Clarified the ATX PLL spacing requirements and listed them in the "ATX PLL Spacing Requirements" table.
2016.09.20 Initial release