AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
Public
Document Table of Contents

1.1.1.2. fPLL

The fPLLs can be used for bonded and non-bonded applications. The fPLLs can access x1, x6, and x24 clock lines. There are no spacing rules between fPLLs regardless of their VCO frequencies.

Figure 4. fPLL Block Diagram