AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
Document Table of Contents ATX PLL

The ATX PLLs can be used for bonded and non-bonded applications. The ATX PLLs can access x1, x6, and x24 clock lines. There are spacing rules between two ATX PLLs running at the same VCO frequency. You can find the VCO frequency by looking at your PLL IP Platform Designer parameter. For more details, refer to Transceiver Clock Network and ATX PLL Spacing Requirements.

Figure 3. ATX PLL Block Diagram