AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

ID 683086
Date 6/24/2022
Document Table of Contents
Give Feedback ATX PLL – fPLL Spacing Requirements

Table 12.  ATX PLL - fPLL Spacing RequirementsWhen using ATX PLL and fPLL operating at the same VCO frequency or within 100 MHz, you must observe the spacing requirements listed in this table.
ATX PLL to fPLL Spacing Spacing Requirement
ATX PLL to fPLL spacing
  • Skip 1 ATX PLL


  • None if fPLL L counter ≥ 2

There are no ATX PLL placement restrictions between two different tiles.

Figure 30. ATX PLL – fPLL Placement Example