AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

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ID 683086
Date 6/24/2022
Public
Document Table of Contents
Document Table of Contents x
1. Transceiver Layout 2. Tile Architecture Constraints 3. PCIe Guidelines 4. Document Revision History for AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage
1. Transceiver Layout x
1.1. L-Tile and H-Tile Overview
1.1. L-Tile and H-Tile Overview x
1.1.1. PLLs 1.1.2. Transmitter Clock Network 1.1.3. GXT Clock Network 1.1.4. Calibration
1.1.1. PLLs x
1.1.1.1. ATX PLL 1.1.1.2. fPLL 1.1.1.3. CMU PLL
1.1.2. Transmitter Clock Network x
1.1.2.1. Bonded Transceiver Channels - Guidelines for VCCR_GXB and VCCT_GXB
2. Tile Architecture Constraints x
2.1. Transceiver Channel Placement 2.2. Unsupported Dynamic Reconfiguration Features 2.3. Intel® Stratix® 10 L-Tile Transceiver to H-Tile Transceiver Migration 2.4. Thermal Guidelines
2.1. Transceiver Channel Placement x
2.1.1. Possible Combinations of GX and GXT Channels 2.1.2. GX Channels 2.1.3. GXT Channels 2.1.4. Bonded Channel Placement with Data Rate Change 2.1.5. Reference Clock Guidelines for L-Tile and H-Tile 2.1.6. PLL Placement
2.1.1. Possible Combinations of GX and GXT Channels x
2.1.1.1. Possible Combinations of GX and GXT Channels in H-Tile 2.1.1.2. Possible Combinations of GX and GXT Channels in L-Tile
2.1.2. GX Channels x
2.1.2.1. Non-bonded GX Channels 2.1.2.2. Bonded GX Channels
2.1.6. PLL Placement x
2.1.6.1. ATX PLL – fPLL Spacing Requirements 2.1.6.2. ATX PLL Usage Model When Driving GXT Channels 2.1.6.3. Simplex Channel Merging 2.1.6.4. TX PLL Restrictions when Using PCIe*
3. PCIe Guidelines x
3.1. PCIe Hard IP 3.2. PHY Interface for PCIe Express (PIPE)
3.1. PCIe Hard IP x
3.1.1. Channel Placement for PCIe Hard IP 3.1.2. PLL Placement for PCIe Hard IP 3.1.3. Non-PCIe and PCIe Hard IP Channel Placement in L-Tile and H-Tile
3.2. PHY Interface for PCIe Express (PIPE) x
3.2.1. Channel Placement for PIPE 3.2.2. PLL Placement for PIPE 3.2.3. Non-PCIe and PCIe PIPE Channel Placement in H-Tile 3.2.4. Non-PCIe and PCIe PIPE Channel Placement in L-Tile
1. Transceiver Layout
2. Tile Architecture Constraints
3. PCIe Guidelines
4. Document Revision History for AN 778: Intel® Stratix® 10 L-Tile/H-Tile Transceiver Usage

2.1.6.1. ATX PLL – fPLL Spacing Requirements

Table 12.  ATX PLL - fPLL Spacing RequirementsWhen using ATX PLL and fPLL operating at the same VCO frequency or within 100 MHz, you must observe the spacing requirements listed in this table.
ATX PLL to fPLL Spacing Spacing Requirement
ATX PLL to fPLL spacing
  • Skip 1 ATX PLL

OR

  • None if fPLL L counter ≥ 2

There are no ATX PLL placement restrictions between two different tiles.

Figure 30. ATX PLL – fPLL Placement Example
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