Intel® FPGA IP for PCIe*
PCI Express (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 gigatransfers per second (GT/s) to 32 GT/s and beyond. Intel® FPGA Intellectual Property (IP) for PCIe continues to scale as the PCI-SIG organization delivers next-generation specifications. Intel has been a member of PCI-SIG since 1992, and with each new generation of silicon, Intel continues to participate in PCI-SIG Compliance Workshops to ensure interoperability and conformance with current industry standards.
Intel® FPGA IP for PCIe*
The PCIe IP solutions include Intel’s PCIe hardened protocol stack, which includes the transaction and data link layers, as well as a hardened physical layer. The later one includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCIe IP also includes optional soft IP blocks, such as Direct Memory Access (DMA) engines and Single-root I/O virtualization (SR-IOV). This unique combination of hardened and soft IP provides superior performance and flexibility for optimal integration.
Intel offers Intel FPGA® IP function-based PCIe IP solutions that have evolved with PCI-SIG’s protocol roadmap.
- Support for up to PCIe 5.0 x16 with R-tile hard IP ›
- Support for up to PCIe 4.0 x16 & 400G Ethernet with F-tile hard IP ›
- Support for up to PCIe 4.0 x16 with P-tile hard IP ›
- Support for up to PCIe 3.0 x16 with L/H-tile hard IP ›
- Support for up to 3x8 with Hard IP on Intel® Arria® 10 and Intel® Cyclone® 10 devices ›
Intel also offers complementary soft IPs, which work with the tile-based hard IPs above for doing PCIe DMA and Switch functions.
Device Support and Number of Hardened PCIe IP Blocks
Device Family |
Number of Hardened PCIe* IP Blocks |
PCIe Link Speed 1.0 (2.5 GT/s) |
PCIe Link Speed 2.0 (5.0 GT/s) |
PCIe Link Speed 3.0 (8.0 GT/s) |
PCIe Link Speed 4.0 (16.0 GT/s) |
PCIe Link Speed 5.0 (32.0 GT/s) |
|---|---|---|---|---|---|---|
Intel® Agilex™ 7 |
1–3 per device |
✓ |
✓ |
✓ |
✓ |
✓ |
Intel® Stratix® 10 |
1–4 per device |
✓ |
✓ |
✓ |
✓ |
|
Intel® Arria® 10 |
1–4 per device |
✓ |
✓ |
✓ |
|
|
Intel® Cyclone® 10 |
1 per device |
✓ |
✓ |
|
|
|
Intel® Cyclone® 10 GX |
1 per device |
✓ |
✓ |
|
|
|
Arria® V |
1–2 per device |
✓ |
✓ |
|
|
|
Cyclone® V GT |
2 per device |
✓ |
✓ |
|
|
|
Cyclone® V GX |
1–2 per device |
✓ |
|
|
|
|
Stratix® IV |
2–4 per device |
✓ |
✓ |
|
|
|
Cyclone® IV GX |
1 per device |
✓ |
|
|
|
|
Arria® II GZ |
1 per device |
✓ |
✓ |
|
|
|
Arria® II GX |
1 per device |
✓ |
|
|
|
|
- CvP – Configuration via Protocol.
- PRoP – Partial Reconfiguration over PCIe.
- SR-IOV – Single Root I/O Virtualization.
- DMA – Direct Memory Access.
Additional Resources
Find IP
Find the right Intel® FPGA Intellectual Property core for your needs.
Technical Support
For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.
IP Evaluation and Purchase
Evaluation mode and purchasing information for Intel® FPGA Intellectual Property cores.
Designing with Intel® FPGA IP
Learn more about designing with Intel® FPGA IP, a large selection of off-the-shelf cores optimized for Intel® FPGAs.
IP Base Suite
Free Intel® FPGA IP Core licenses with an active license for Intel® Quartus® Prime Standard or Pro Edition Software.
Design Examples
Download design examples and reference designs for Intel® FPGA devices.
Contact Sales
Get in touch with sales for your Intel® FPGA product design and acceleration needs.