Intel® FPGA IP for PCI* Express

PCI Express (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 gigatransfers per second (GT/s) to 32 GT/s and beyond. Intel FPGA Intellectual Property (IP) for PCI Express continues to scale as the PCI-SIG organization delivers next-generation specifications. Intel has been a member of PCI-SIG since 1992, and with each new generation of silicon, Intel continues to participate in PCI-SIG Compliance Workshops to ensure interoperability and conformance with current industry standards.

Intel® FPGA IP for PCI* Express

F-TILE PCIE HARD IP

The PCI Express IP solutions include Intel’s technology-leading PCI Express hardened protocol stack, which includes the transaction and data link layers, as well as a hardened physical layer. The later one includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCI Express IP also includes optional soft IP blocks, such as Direct Memory Access (DMA) engines and Single-root I/O virtualization (SR-IOV). This unique combination of hardened and soft IP provides superior performance and flexibility for optimal integration.

Intel offers Intel FPGA IP function-based PCI Express IP solutions that are compliant with the Platform Designer (formerly Qsys). Intel FPGA IP offerings have evolved to be in sync with PCI-SIG’s PCI Express protocol roadmap.

Intel also offers Companion soft IPs, which work with the tile-based hard IPs above for doing PCI Express DMA and Switch functions.

Device Support and Number of Hardened PCI Express IP Blocks

Device Family

Number of Hardened PCI Express* IP Blocks

PCI Express Link Speed

Gen1 (2.5 GT/s)

PCI Express Link Speed

Gen2 (5.0 GT/s)

PCI Express Link Speed

Gen3 (8.0 GT/s)

PCI Express Link Speed

Gen4 (16.0 GT/s)

PCI Express Link Speed

Gen5 (32.0 GT/s)

Intel® Agilex™

1–3 per device

Intel® Stratix® 10

1–4 per device

 

Intel Arria 10

1–4 per device

 

 

Intel Cyclone 10

1 per device

 

 

 

Intel® Cyclone® 10 GX

1 per device

 

 

 

Arria® V

1–2 per device

 

 

 

Cyclone® V GT

2 per device

 

 

 

Cyclone® V GX

1–2 per device

 

 

 

 

Stratix® IV

2–4 per device

 

 

 

Cyclone® IV GX

1 per device

 

 

 

 

Arria® II GZ

1 per device

 

 

 

Arria® II GX

1 per device

 

 

 

 

Device Configurations and Features Support

Interface Type

Avalon® streaming interface

Avalon® memory mapped

Avalon memory mapped with DMA

SR-IOV

CvP / PRoP

Device/Configuration

 

Intel Agilex

Endpoint

Up to Gen5 x16

Up to Gen5 x16

Up to Gen5 x16

Available

Up to Gen5 x16: CVP Init

Root Port

Up to Gen5 x16

Up to Gen5 x16

-

-

-

Intel Stratix 10

Endpoint

Up to Gen4 x16

Up to Gen4 x16

Up to Gen4 x16

Available

Up to Gen4 x16: CVP Init

Root Port

Up to Gen4 x16

Up to Gen4 x16

-

-

-

Intel® Arria 10

Endpoint

Up to Gen3 x8

Up to Gen3 x4

Gen1 x8, Gen2 x4, Gen2 x8, Gen3 x2, Gen3 x4, Gen3 x8

Available

Up to Gen3 x8: CVP and PRoP

Root Port

Up to Gen3 x8

Up to Gen3 x4

-

-

-

Intel Cyclone 10 GX

Endpoint

Up to Gen2 x4

Up to Gen2 x4

Gen2 x4

-

Up to Gen2 x4: CVP and PRoP

Root Port

Up to Gen2 x4

Up to Gen2 x4

-

-

-

Stratix® V

Endpoint

Up to Gen3 x8

Up to Gen3 x4

Gen1 x8, Gen2 x4, Gen2 x8
Gen3 x2, Gen3 x4, Gen3 x8

Available

Gen1: CVP Init and CVP Update
Gen2: CVP Init and CVP Update

Root Port

Up to Gen3 x8

Up to Gen3 x4

-

-

-

Arria® V GZ

Endpoint

Up to Gen3 x8

Up to Gen3 x4

Gen1 x8, Gen2 x4, Gen2 x8
Gen3 x2, Gen3 x4, Gen3 x8

-

Gen1: CVP Init and CVP Update
Gen2: CVP Init and CVP Update

Root Port

Up to Gen3 x8

Up to Gen3 x4

-

-

-

Arria V

Endpoint

Up to Gen1 x8 and Gen2 x4

Up to Gen1 x8 and

Gen2 x4 (no x2)

Gen1 x8, Gen2 x4

-

Up to Gen1 x8 and Gen2 x4
Gen1: CVP Init and CVP Update
Gen2: CVP Init

Root Port

Up to Gen1 x8 and Gen2 x4

Up to Gen1 x8 and

Gen2 x4 (no x2)

-

-

-

Cyclone® V

Endpoint

Up to Gen2 x4

Up to Gen2 x4 (no x2)

Gen2 x4

-

Up to Gen2 x4
Gen1: CVP Init and CVP Update
Gen2: CVP Init

Root Port

Up to Gen2 x4

Up to Gen2 x4 (no x2)

-

-

-

  • CvP – Configuration via Protocol
  • PRoP – Partial Reconfiguration over PCI Express
  • SR-IOV – Single Root I/O Virtualization
  • DMA – Direct Memory Access

Product and Performance Information

1

Retail prices reported as of 25 Jan 2022 04:56:53 GMT