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  1. Intel® Products
  2. Altera® FPGA, SoC FPGA and CPLD
  3. Altera® FPGA Intellectual Property
  4. Interface Protocols IP Cores
  5. PCIe Intel® FPGA IP

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Intel® FPGA IP for PCIe

PCI Express (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 gigatransfers per second (GT/s) to 32 GT/s and beyond. Intel® FPGA Intellectual Property (IP) for PCIe continues to scale as the PCI-SIG organization delivers next-generation specifications. Intel has been a member of PCI-SIG since 1992, and with each new generation of silicon, Intel continues to participate in PCI-SIG Compliance Workshops to ensure interoperability and conformance with current industry standards.

The PCIe IP solutions include a PCIe hardened protocol stack, which includes the transaction and data link layers, as well as a hardened physical layer. The latter one includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Our PCIe IP portfolio also includes optional soft IP blocks, such as Direct Memory Access (DMA) engines and PCIe Switch. This unique combination of hardened and soft IP provides superior performance and flexibility for optimal integration.

Intel FPGA IP function-based PCIe IP solutions have evolved with PCI-SIG’s protocol roadmap.

  • Support for up to PCIe 4.0 x8 with GTS PCIe Hard IP ›
  • Support for up to PCIe 5.0 x16 with R-Tile PCIe Hard IP ›
  • Support for up to PCIe 4.0 x16 & 400G Ethernet with F-Tile PCIe Hard IP ›
  • Support for up to PCIe 4.0 x16 with P-Tile PCIe Hard IP ›
  • Support for up to PCIe 3.0 x16 with L/H-Tile PCIe Hard IP ›
  • Support for up to 3x8 with Hard IP on Arria® 10 and Cyclone® 10 devices ›

Our complementary soft IPs work with the PCIe Hard IPs above for doing PCIe DMA and Switch functions.

  • Agilex™ 5 FPGA – GTS AXI Multichannel DMA IP (AXI-Stream Interface) available to complement the GTS PCIe Hard IP ›
  • Agilex™ 7 FPGA – AXI Multichannel DMA IP (AXI-Stream Interface) available to complement R-Tile PCIe Hard IP ›
  • Agilex™ 7 and Stratix® 10 FPGAs – Multichannel DMA IP (AVMM / AVST Interfaces) available to complement H-Tile (Stratix® 10)/P-Tile/F-Tile/R-Tile PCIe Hard IP ›
  • Scalable PCIe Switch IP available to complement P-Tile/F-Tile/R-Tile PCIe Hard IP ›

Device Support and Number of PCIe IP Blocks

Device Family

Number of PCIe IP Blocks

PCIe Link Speed

1.0 (2.5 GT/s)

PCIe Link Speed

2.0 (5.0 GT/s)

PCIe Link Speed

3.0 (8.0 GT/s)

PCIe Link Speed

4.0 (16.0 GT/s)

PCIe Link Speed

5.0 (32.0 GT/s)
Agilex™ 7 1–4 per device ✓ ✓ ✓ ✓ ✓
Agilex™ 5 1 - 4 per device ✓ ✓ ✓ ✓  
Agilex™ 3 1 per device ✓ ✓ ✓    
Stratix® 10 1–4 per device ✓ ✓ ✓ ✓

 

Arria® 10 1–4 per device ✓ ✓ ✓

 

 

Cyclone® 10 1 per device ✓ ✓

 

 

 

Cyclone® 10 GX 1 per device ✓ ✓

 

 

 

Arria® V 1–2 per device ✓ ✓

 

 

 

Cyclone® V GT 2 per device ✓ ✓

 

 

 

Cyclone® V GX 1–2 per device ✓

 

 

 

 

Stratix® IV 2–4 per device ✓ ✓

 

 

 

Cyclone® IV GX 1 per device ✓

 

 

 

 

Arria® II GZ 1 per device ✓ ✓

 

 

 

Arria® II GX 1 per device ✓

 

 

 

 

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Additional Resources

Find IP

Find the right Altera® FPGA Intellectual Property core for your needs.

Technical Support

For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.

IP Evaluation and Purchase

Evaluation mode and purchasing information for Altera® FPGA Intellectual Property cores.

IP Base Suite

Free Altera® FPGA IP Core licenses with an active license for Quartus® Prime Standard or Pro Edition Software.

Design Examples

Download design examples and reference designs for Altera® FPGA devices.

Contact Sales

Get in touch with sales for your Altera® FPGA product design and acceleration needs.

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