PCIe* Multi Channel DMA IP and AVMM Bridge IP

The Multi Channel DMA for PCIe IP enables you to efficiently transfer data between the host and device. The Multi Channel DMA for PCIe IP supports multiple DMA channels between the host and device over the underlying PCIe* link.

Read the Multi Channel DMA Intel® FPGA IP for PCIe user guide ›

Read the Multi Channel DMA for PCIe Intel® FPGA IP Design Example user guide ›

PCIe* Multi Channel DMA IP and AVMM Bridge IP

IP Quality Metrics

Basics

Year IP was first released

2020

Status

Production

Deliverables

Customer deliverables include the following:

Design file (encrypted source code or post-synthesis netlist)

Timing and/or layout constraints

Documentation with revision control

Yes for all

Any additional customer deliverables provided with IP

Testbench and Example Designs

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

Verilog

Software drivers provided

Y

Driver OS Support

Linux*

Implementation

User interface

Avalon streaming interface, Avalon memory mapped

IP-XACT metadata

Y

Verification

Simulators supported

VCS

Hardware validated

Intel Stratix 10 development kit, Intel Agilex P-tile development kit

Industry standard compliance testing performed

N/A

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

N/A

If yes, on which Intel FPGA device(s)

N/A

Interoperability reports available

N/A