The Multi Channel DMA for PCIe IP enables you to efficiently transfer data between the host and device. The Multi Channel DMA for PCIe IP supports multiple DMA channels between the host and device over the underlying PCIe* link.
A DMA channel consists of Host to Device (H2D) and Device to Host (D2H) queue pair. As shown in the figure, the Multi Channel DMA for PCIe IP can be used in a server’s hardware infrastructure to allow communication between various Virtual Machine (VM) based clients and their FPGA-device based counterparts. The Multi-Channel DMA for PCIe operates on descriptor-based queues set up by driver software to transfer data between local FPGA and host. Multi Channel DMA for PCIe IP’s control logic reads the queue descriptors and executes them. Separate queues are used for D2H and H2D operations for each channel. The Multi Channel DMA for PCIe IP integrates the Intel® PCIe Hard IP and interfaces with the host Root Complex via the PCIe link. On the user logic side, Avalon® memory mapped and Avalon® streaming interfaces of the IP allow for easy integration of the MCDMA IP with other Platform Designer components.
The Multi channel DMA IP also incorporates AVMM (Avalon® Memory mapped) bridge functionality for both Endpoint & Rootport configurations as shown in the figure. Users can avail of the bridge functionality in a standalone fashion or in conjunction with the MCDMA module.
Option to select Avalon® memory-mapped interface or Avalon® streaming interface user logic interface.
Supports for up to 2048 channels with SR-IOV support (8 PFs / 2K VFs).
Inbuilt architecture to prevent Head-of-line blocking on any channel.
Per-Descriptor completion notification with Writeback or MSI.
Support for Max Payload Size value of 512 bytes.
Support for Completion Re-ordering.
Multi-Channel DMA Intel® FPGA IP for PCI Express (available with H-Tile, P-Tile, and F-Tile)