PCIe* Multi Channel DMA IP and AVMM Bridge IP
The Multi Channel DMA for PCIe IP enables you to efficiently transfer data between the host and device. The Multi Channel DMA for PCIe IP supports multiple DMA channels between the host and device over the underlying PCIe* link.
Read the Multi Channel DMA Intel® FPGA IP for PCIe user guide ›
Read the Multi Channel DMA for PCIe Intel® FPGA IP Design Example user guide ›
PCIe* Multi Channel DMA IP and AVMM Bridge IP
A DMA channel consists of Host to Device (H2D) and Device to Host (D2H) queue pair. As shown in the figure, the Multi Channel DMA for PCIe IP can be used in a server’s hardware infrastructure to allow communication between various Virtual Machine (VM) based clients and their FPGA-device based counterparts. The Multi-Channel DMA for PCIe operates on descriptor-based queues set up by driver software to transfer data between local FPGA and host. Multi Channel DMA for PCIe IP’s control logic reads the queue descriptors and executes them. Separate queues are used for D2H and H2D operations for each channel. The Multi Channel DMA for PCIe IP integrates the Intel® PCIe Hard IP and interfaces with the host Root Complex via the PCIe link. On the user logic side, Avalon® memory mapped and Avalon® streaming interfaces of the IP allow for easy integration of the MCDMA IP with other Platform Designer components.
The Multi channel DMA IP also incorporates AVMM (Avalon® Memory mapped) bridge functionality for both Endpoint & Rootport configurations as shown in the figure. Users can avail of the bridge functionality in a standalone fashion or in conjunction with the MCDMA module.
Features
- Option to select Avalon® memory-mapped interface or Avalon® streaming interface user logic interface.
- Supports for up to 2048 channels with SR-IOV support (8 PFs / 2K VFs).
- Inbuilt architecture to prevent Head-of-line blocking on any channel.
- Per-Descriptor completion notification with Writeback or MSI.
- Support for Max Payload Size value of 512 bytes.
- Support for Completion Re-ordering.
IP Quality Metrics
Basics |
|
|---|---|
Year IP was first released |
2020 |
Status |
Production |
Deliverables |
|
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Timing and/or layout constraints Documentation with revision control |
Yes for all |
Any additional customer deliverables provided with IP |
Testbench and Example Designs |
Parameterization GUI allowing end user to configure IP |
Y |
IP core is enabled for Intel FPGA IP Evaluation Mode Support |
Y |
Source language |
Verilog |
Testbench language |
Verilog |
Software drivers provided |
Y |
Driver OS Support |
Linux* |
Implementation |
|
User interface |
Avalon streaming interface, Avalon memory mapped |
IP-XACT metadata |
Y |
Verification |
|
Simulators supported |
VCS |
Hardware validated |
Intel Stratix 10 development kit, Intel Agilex P-tile development kit |
Industry standard compliance testing performed |
N/A |
If Yes, which test(s)? |
N/A |
If Yes, on which Intel FPGA device(s)? |
N/A |
If Yes, date performed |
N/A |
If No, is it planned? |
N/A |
Interoperability |
|
IP has undergone interoperability testing |
N/A |
If yes, on which Intel FPGA device(s) |
N/A |
Interoperability reports available |
N/A |
Related Links
Documentation
Device and Hardware Development Kit Support
Additional Resources
Find IP
Find the right Intel® FPGA Intellectual Property core for your needs.
Technical Support
For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.
IP Evaluation and Purchase
Evaluation mode and purchasing information for Intel® FPGA Intellectual Property cores.
Designing with Intel® FPGA IP
Learn more about designing with Intel® FPGA IP, a large selection of off-the-shelf cores optimized for Intel® FPGAs.
IP Base Suite
Free Intel® FPGA IP Core licenses with an active license for Intel® Quartus® Prime Standard or Pro Edition Software.
I-Tested
Intel awards the interoperability-tested or I-Tested certification to verified Intel® FPGA IP or Intel® FPGA Design Solutions Network member IP cores.
Intel® FPGA Partner IP
Browse catalog of Intel® FPGA partner intellectual property cores in the Intel® Solutions Marketplace.
Design Examples
Download design examples and reference designs for Intel® FPGA devices.
IP Certifications
Intel is committed to providing Intellectual Property cores that work seamlessly with Intel® FPGA tools or interface specifications.
Contact Sales
Get in touch with sales for your Intel® FPGA product design and acceleration needs.