GTS PCIe Hard IP

Agilex™ 5 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller IP supporting up to PCIe 4.0 x8 configurations for Root Port (RP), Endpoint (EP), and Transaction Layer (TL) bypass modes.

Agilex™ 3 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller IP supporting up to PCIe 3.0 x4 configurations for Root Port and Endpoint modes.

GTS PCIe Hard IP for PCI Express* Greatly Simplifies Design Integration for a Broad Range of Applications

  • Hardened IP blocks reduce logic resourcing allowing for higher user logic integration
  • Hardened IP blocks (complete protocol stack)
    • Transaction Layer / Data Link Layer / PHY Layer (MAC), and PHY (PCS and PMA)
    • SR-IOV (4 PFs, 256 VFs) enabling multiple applications on a single server - reducing Total Cost of Ownership (TCO)
  • Faster timing closure decreases time-to-market design cycles
  • Easy-to-use Design Tool Kit (DTK) for diagnostic and debug testing of PCIe design

  • Full protocol stack, including the Transaction, Data Link, and Physical Layers, implemented as Hard IP
    • Agilex 5 FPGA: Up to 4.0 x8 support: (Root Port (RP), Endpoint (EP), and Transaction Layer (TL) bypass modes)
    • Agilex 3 FPGA: Up to 3.0 x4 support (Root Port and Endpoint modes)
  • Agilex 5 FPGA: PCIe 3.0/4.0 (x8/x4/x2/x1) configurations with 1.0/2.0 configurations support via link down-training support
  • Agilex 3 FPGA: PCIe 3.0 (x4/x2/x1) configurations with 1.0/2.0 configurations support via link down-training support
  • Separate reference clock with independent spread spectrum clocking (SRIS)
    • Separate reference clock with no spread spectrum clocking (SRNS)
  • Independent PERST#
  • Single Virtual Channel (VC)
  • Capability Registers
  • 512-byte Maximum Payload Size (MPS)
  • 4096-byte (4 KB) Maximum Read Request Size (MRRS)
  • 32/64-bit BAR support (Prefetchable/Non-Prefetchable)

  • Expansion ROM BAR support
  • Number of tags for x8 controller: 32/64/128/256/512 (Agilex 5 FPGA)
  • Number of tags for x4 controller: 32/64/128/256 (Agilex 5 and Agilex 3 FPGAs)
  • MSI-X Table (maximum 4096 across)
  • Atomic operations (Fetch/Add/Swap/CAS)
  • TL Bypass mode allows for optional 3rd-party PCIe switch IP integration (Agilex 5 FPGA)
  • Precision Time Measurement (PTM)
  • SR-IOV support (4 PFs, 256 VFs)
    • Function Level Reset (FLR)
  • VirtIO support for software-based virtualization
  • SpyGlass CDC analysis tool
  • AXI4-Stream for application data path
    • AXI4-Stream Source/Sink
  • AXI-Lite for control and status register responder interface

Agilex™ 5 FPGAs In-Action PCI Express IP Demo Video

  • Hardware acceleration
  • Artificial Intelligence (AI) / Machine Learning (ML)
  • Networking
  • Virtualization
  • Compute and Storage
  • Embedded

IP

Included in Quartus® Prime Design Software

Ordering Codes

GTS AXI Streaming Intel FPGA IP for PCI Express

Yes

No ordering code required
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