GTS AXI Streaming IP for PCI Express* Design Example User Guide

Download PDF
ID 817713
Date 10/23/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming IP for PCI Express* Design Example User Guide A. Appendix
1. About the GTS AXI Streaming IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description 1.3. Single-Root I/O Virtualization (SR-IOV) Design Example 1.4. Performance Design Example
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks IP 1.2.5. GTS Reset Sequencer IP 1.2.6. Reset Release IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. Transmit Flow Control 1.2.2.7. AXI-S to Avalon® -ST Adapter 1.2.2.8. Soft Reset Controller
1.3. Single-Root I/O Virtualization (SR-IOV) Design Example x
1.3.1. Single-Root I/O Virtualization (SR-IOV) Design Example Functional Description
1.4. Performance Design Example x
1.4.1. Performance Design Example Functional Description
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example 2.6. Hardware and Software Requirements 2.7. Program the FPGA 2.8. Installing the Linux Kernel Driver 2.9. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* MX 2.3.2. Steps to Run Simulation using QuestaSIM* 2.3.3. Steps to Run Simulation using Xcelium* 2.3.4. Steps to Run Simulation using Riviera-PRO*
2.3.1. Steps to Run Simulation using VCS* MX x
2.3.1.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. Root Port BFM 2.4.3. PIO Design Example Testbench 2.4.4. Single Root I/O Virtualization (SR-IOV) Design Example Testbench 2.4.5. Performance Design Example Testbench
2.4.2. Root Port BFM x
2.4.2.1. BFM Memory Map 2.4.2.2. Configuration Space Bus and Device Numbering 2.4.2.3. Configuration of Root Port and Endpoint 2.4.2.4. Issuing Read and Write Transactions to the Application Layer
2.9. Running the Design Example x
2.9.1. Running the PIO Design Example 2.9.2. Running the Single Root I/O Virtualization (SR-IOV) Design Example
A. Appendix x
A.1. BFM Procedures and Functions
A.1. BFM Procedures and Functions x
A.1.1. ebfm_barwr Procedure A.1.2. ebfm_barwr_imm Procedure A.1.3. ebfm_barrd_wait Procedure A.1.4. ebfm_barrd_nowt Procedure A.1.5. ebfm_cfgwr_imm_wait Procedure A.1.6. ebfm_cfgwr_imm_nowt Procedure A.1.7. ebfm_cfgrd_wait Procedure A.1.8. ebfm_cfgrd_nowt Procedure A.1.9. BFM Configuration Procedures A.1.10. BFM Shared Memory Access Procedures A.1.11. BFM Log and Message Procedures A.1.12. Verilog HDL Formatting Functions
A.1.9. BFM Configuration Procedures x
A.1.9.1. ebfm_cfg_rp_ep Procedure A.1.9.2. ebfm_cfg_decode_bar Procedure
A.1.10. BFM Shared Memory Access Procedures x
A.1.10.1. Shared Memory Constants A.1.10.2. shmem_write Task A.1.10.3. shmem_read Function A.1.10.4. shmem_display Verilog HDL Function A.1.10.5. shmem_fill Procedure A.1.10.6. shmem_chk_ok Function
A.1.11. BFM Log and Message Procedures x
A.1.11.1. ebfm_display Verilog HDL Function A.1.11.2. ebfm_log_stop_sim Verilog HDL Function A.1.11.3. ebfm_log_set_suppressed_msg_mask Task A.1.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task A.1.11.5. ebfm_log_open Verilog HDL Function A.1.11.6. ebfm_log_close Verilog HDL Function
A.1.12. Verilog HDL Formatting Functions x
A.1.12.1. himage1 A.1.12.2. himage2 A.1.12.3. himage4 A.1.12.4. himage8 A.1.12.5. himage16 A.1.12.6. dimage1 A.1.12.7. dimage2 A.1.12.8. dimage3 A.1.12.9. dimage4 A.1.12.10. dimage5 A.1.12.11. dimage6 A.1.12.12. dimage7
1. About the GTS AXI Streaming IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming IP for PCI Express* Design Example User Guide
A. Appendix

1. About the GTS AXI Streaming IP for PCI Express* Design Example

Updated for:
Intel® Quartus® Prime Design Suite 25.3
IP Version 9.1.0

GTS AXI Streaming IP for PCI Express* design example is a simple design to demonstrate the establishment of the PCI Express* connectivity of the Agilex™ 3 and Agilex™ 5 FPGAs in Quartus® Prime software. The PCIe* system host CPU uses Programmed Input/Output (PIO) transactions to access memory map locations in the design example through the PCIe* link. The Programmed Input/ Output (PIO) application block is needed to handle the translation from PCIe* TLP to Avalon® memory-mapped interface protocol of the on-chip memory.

Attention:
  1. Any occurrence of GTS AXI Streaming IP throughout this document shall constitute a reference to the GTS AXI Streaming IP for PCI Express* .
  2. Any occurrence of PCIe* Gen4 or Gen4 throughout this document shall constitute a reference to the PCIe* 4.0.
Table 1.   GTS AXI Streaming IP for PCI Express* Design Examples
Device Design Example Hard IP Mode Simulation Hardware
Agilex™ 5

PIO

Gen4x4 Interface 256-bit Endpoint

Supports VCS* MX, QuestaSIM* , Questa*-Altera® FPGA Edition, Xcelium* , and Riviera-PRO* simulators.

No Support
PIO

Gen3x4 Interface 128-bit Endpoint

 Agilex™ 5 FPGA E-Series 065B Modular Development Kit (ES1)
PIO Gen3x1 Interface 128-bit Endpoint No Support
PIO

Gen4x8 Interface 512-bit Endpoint
No Support
Note: This design example variant is only supported in Agilex™ 5 D-Series FPGAs.
SR-IOV

Gen3x4 Interface 128-bit Endpoint

 Agilex™ 5 FPGA E-Series 065B Modular Development Kit (ES1)
SR-IOV Gen4x8 Interface 512-bit Endpoint No Support
Note: This design example variant is only supported in Agilex™ 5 D-Series FPGAs.
Performance Design

Gen4x4 Interface 256-bit Endpoint

No Support
Agilex™ 3 PIO

Gen3x4 Interface 128-bit Endpoint

No Support
PIO

Gen3x1 Interface 128-bit Endpoint

Agilex™ 3 FPGA C-Series 135B Non-HPS Development Kit (Production)
SR-IOV Gen3x4 Interface 128-bit Endpoint No Support
Important:
  1. Design examples only support the default settings in the parameter editor of the GTS AXI Streaming IP in the Quartus® Prime software.
  2. Design examples do not support the 10-bit tag completer feature. Running the design example on the host machine enforces a 10-bit tag at PCIe* Gen4 and can cause completion timeout or system crashes.
  3. You cannot validate the GTS AXI Streaming IP configured with a x1 link on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit due to the reversed PCIe* lane on the board.

Section Content
Programmed Input/Output Design Example
Programmed Input/Output Design Example Functional Description
Single-Root I/O Virtualization (SR-IOV) Design Example
Performance Design Example

Related Information
Level Two Title