GTS AXI Streaming IP for PCI Express* Design Example User Guide

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ID 817713
Date 10/23/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming IP for PCI Express* Design Example User Guide A. Appendix
1. About the GTS AXI Streaming IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description 1.3. Single-Root I/O Virtualization (SR-IOV) Design Example 1.4. Performance Design Example
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks IP 1.2.5. GTS Reset Sequencer IP 1.2.6. Reset Release IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. Transmit Flow Control 1.2.2.7. AXI-S to Avalon® -ST Adapter 1.2.2.8. Soft Reset Controller
1.3. Single-Root I/O Virtualization (SR-IOV) Design Example x
1.3.1. Single-Root I/O Virtualization (SR-IOV) Design Example Functional Description
1.4. Performance Design Example x
1.4.1. Performance Design Example Functional Description
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example 2.6. Hardware and Software Requirements 2.7. Program the FPGA 2.8. Installing the Linux Kernel Driver 2.9. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* MX 2.3.2. Steps to Run Simulation using QuestaSIM* 2.3.3. Steps to Run Simulation using Xcelium* 2.3.4. Steps to Run Simulation using Riviera-PRO*
2.3.1. Steps to Run Simulation using VCS* MX x
2.3.1.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. Root Port BFM 2.4.3. PIO Design Example Testbench 2.4.4. Single Root I/O Virtualization (SR-IOV) Design Example Testbench 2.4.5. Performance Design Example Testbench
2.4.2. Root Port BFM x
2.4.2.1. BFM Memory Map 2.4.2.2. Configuration Space Bus and Device Numbering 2.4.2.3. Configuration of Root Port and Endpoint 2.4.2.4. Issuing Read and Write Transactions to the Application Layer
2.9. Running the Design Example x
2.9.1. Running the PIO Design Example 2.9.2. Running the Single Root I/O Virtualization (SR-IOV) Design Example
A. Appendix x
A.1. BFM Procedures and Functions
A.1. BFM Procedures and Functions x
A.1.1. ebfm_barwr Procedure A.1.2. ebfm_barwr_imm Procedure A.1.3. ebfm_barrd_wait Procedure A.1.4. ebfm_barrd_nowt Procedure A.1.5. ebfm_cfgwr_imm_wait Procedure A.1.6. ebfm_cfgwr_imm_nowt Procedure A.1.7. ebfm_cfgrd_wait Procedure A.1.8. ebfm_cfgrd_nowt Procedure A.1.9. BFM Configuration Procedures A.1.10. BFM Shared Memory Access Procedures A.1.11. BFM Log and Message Procedures A.1.12. Verilog HDL Formatting Functions
A.1.9. BFM Configuration Procedures x
A.1.9.1. ebfm_cfg_rp_ep Procedure A.1.9.2. ebfm_cfg_decode_bar Procedure
A.1.10. BFM Shared Memory Access Procedures x
A.1.10.1. Shared Memory Constants A.1.10.2. shmem_write Task A.1.10.3. shmem_read Function A.1.10.4. shmem_display Verilog HDL Function A.1.10.5. shmem_fill Procedure A.1.10.6. shmem_chk_ok Function
A.1.11. BFM Log and Message Procedures x
A.1.11.1. ebfm_display Verilog HDL Function A.1.11.2. ebfm_log_stop_sim Verilog HDL Function A.1.11.3. ebfm_log_set_suppressed_msg_mask Task A.1.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task A.1.11.5. ebfm_log_open Verilog HDL Function A.1.11.6. ebfm_log_close Verilog HDL Function
A.1.12. Verilog HDL Formatting Functions x
A.1.12.1. himage1 A.1.12.2. himage2 A.1.12.3. himage4 A.1.12.4. himage8 A.1.12.5. himage16 A.1.12.6. dimage1 A.1.12.7. dimage2 A.1.12.8. dimage3 A.1.12.9. dimage4 A.1.12.10. dimage5 A.1.12.11. dimage6 A.1.12.12. dimage7
1. About the GTS AXI Streaming IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming IP for PCI Express* Design Example User Guide
A. Appendix

1.3.1. Single-Root I/O Virtualization (SR-IOV) Design Example Functional Description

Figure 6.  Platform Designer System Contents for the GTS AXI Streaming IP Single-Root I/O Virtualization Design Example
This design example includes the following components:
  1. The DUT component is the GTS AXI Streaming IP for PCI Express configured as an Endpoint interacting with the root complex/switch on one end, and drives the received TLP data to the SR-IOV application at the other end. The DUT component translates the PCIe serial link transfer interface to the AXI Stream interface.
  2. The SR-IOV Design Example for GTS AXI Streaming IP component interfaces with the DUT through the AXI Stream interface. It initiates a series of RAMs to store the incoming data from the DUT. The number of RAM is determined by PF and VF from the user. During operation modes, the SR-IOV Design Example for GTS AXI Streaming IP decodes the TLP headers/data into Memory write or Memory read instructions. If the instructions are valid, Memory write or Memory read is performed to the PF and VF Segram according to the PF and VF information from the AXI Stream interface with DUT, which performs the necessary translation between the PCI Express TLPs and simple AXI Stream writes and reads to the on-chip memory.
    1. Access Parser

      Access Parser is a submodule to decode and validate the incoming instruction, whether it is valid and good to proceed to the next phase of processing. It ensures the target address and data are double-word aligned. If the received Memory write instruction does not fulfill the requirement, it is silently dropped. While for Memory read instruction, which does not fulfill the requirement, it will be a Completer Abort.

    2. Access Router

      Access Router is a network of connections that connects all the instantiated Segrams. It reroutes the data from the source to the target destination. Based on the decoded PF and VF information from the Access Parser, the targeted Segram activates, and does further processing.

    3. Completion

      The Completion submodule stores the necessary header information from the incoming Memory read instruction and repackages the acquired information into a CplD header. The CplD header is released together with the fetched data from the targeted Segram.

    4. PF Segram

      The PF Segram is a RAM instantiated from the design example based on the PF number. Each RAM instantiated consists of 64-bit data width and is 64 deep, for a total of 4 KB.

    5. VF Segram

      The VF Segram is a RAM instantiated from the SR-IOV Design Example based on the PF and VF number. Each RAM instantiated consists of a 64-bit data width and is 64 deep, for a total of 4 KB.

  3. Transmit Flow Control
    Note: Refer to Transmit Flow Control for additional information.
  4. Soft Reset Controller
    Note: Refer to Soft Reset Controller for additional information.
  5. AXI-S to Avalon-ST Adapter
    Note: Refer to AXI-S to Avalon-ST Adapter for additional information.
  6. GTS System PLL Clocks IP
    Note: Refer to GTS System PLL Clocks IP for additional information.
  7. GTS Reset Sequencer IP
    Note: Refer to GTS Reset Sequencer IP for additional information.
  8. Reset Release IP
    Note: Refer to Reset Release IP for additional information.
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