GTS AXI Streaming IP for PCI Express* Design Example User Guide

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ID 817713
Date 10/23/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS AXI Streaming IP for PCI Express* Design Example 2. Quick Start Guide 3. Document Revision History for the GTS AXI Streaming IP for PCI Express* Design Example User Guide A. Appendix
1. About the GTS AXI Streaming IP for PCI Express* Design Example x
1.1. Programmed Input/Output Design Example 1.2. Programmed Input/Output Design Example Functional Description 1.3. Single-Root I/O Virtualization (SR-IOV) Design Example 1.4. Performance Design Example
1.2. Programmed Input/Output Design Example Functional Description x
1.2.1. GTS AXI Streaming IP—Design Under Test (DUT) 1.2.2. PIO Application 1.2.3. On-Chip Memory (MEM) 1.2.4. GTS System PLL Clocks IP 1.2.5. GTS Reset Sequencer IP 1.2.6. Reset Release IP
1.2.2. PIO Application x
1.2.2.1. Scheduler 1.2.2.2. Read Write Module 1.2.2.3. Avalon® Memory-Mapped Interface 1.2.2.4. Completion Module 1.2.2.5. Width Adapter 1.2.2.6. Transmit Flow Control 1.2.2.7. AXI-S to Avalon® -ST Adapter 1.2.2.8. Soft Reset Controller
1.3. Single-Root I/O Virtualization (SR-IOV) Design Example x
1.3.1. Single-Root I/O Virtualization (SR-IOV) Design Example Functional Description
1.4. Performance Design Example x
1.4.1. Performance Design Example Functional Description
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Design Example Simulation Testbench 2.5. Compiling the Design Example 2.6. Hardware and Software Requirements 2.7. Program the FPGA 2.8. Installing the Linux Kernel Driver 2.9. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Steps to Run Simulation using VCS* MX 2.3.2. Steps to Run Simulation using QuestaSIM* 2.3.3. Steps to Run Simulation using Xcelium* 2.3.4. Steps to Run Simulation using Riviera-PRO*
2.3.1. Steps to Run Simulation using VCS* MX x
2.3.1.1. Running VCS* MX Simulation in Interactive Mode
2.4. Design Example Simulation Testbench x
2.4.1. Test Driver Module 2.4.2. Root Port BFM 2.4.3. PIO Design Example Testbench 2.4.4. Single Root I/O Virtualization (SR-IOV) Design Example Testbench 2.4.5. Performance Design Example Testbench
2.4.2. Root Port BFM x
2.4.2.1. BFM Memory Map 2.4.2.2. Configuration Space Bus and Device Numbering 2.4.2.3. Configuration of Root Port and Endpoint 2.4.2.4. Issuing Read and Write Transactions to the Application Layer
2.9. Running the Design Example x
2.9.1. Running the PIO Design Example 2.9.2. Running the Single Root I/O Virtualization (SR-IOV) Design Example
A. Appendix x
A.1. BFM Procedures and Functions
A.1. BFM Procedures and Functions x
A.1.1. ebfm_barwr Procedure A.1.2. ebfm_barwr_imm Procedure A.1.3. ebfm_barrd_wait Procedure A.1.4. ebfm_barrd_nowt Procedure A.1.5. ebfm_cfgwr_imm_wait Procedure A.1.6. ebfm_cfgwr_imm_nowt Procedure A.1.7. ebfm_cfgrd_wait Procedure A.1.8. ebfm_cfgrd_nowt Procedure A.1.9. BFM Configuration Procedures A.1.10. BFM Shared Memory Access Procedures A.1.11. BFM Log and Message Procedures A.1.12. Verilog HDL Formatting Functions
A.1.9. BFM Configuration Procedures x
A.1.9.1. ebfm_cfg_rp_ep Procedure A.1.9.2. ebfm_cfg_decode_bar Procedure
A.1.10. BFM Shared Memory Access Procedures x
A.1.10.1. Shared Memory Constants A.1.10.2. shmem_write Task A.1.10.3. shmem_read Function A.1.10.4. shmem_display Verilog HDL Function A.1.10.5. shmem_fill Procedure A.1.10.6. shmem_chk_ok Function
A.1.11. BFM Log and Message Procedures x
A.1.11.1. ebfm_display Verilog HDL Function A.1.11.2. ebfm_log_stop_sim Verilog HDL Function A.1.11.3. ebfm_log_set_suppressed_msg_mask Task A.1.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task A.1.11.5. ebfm_log_open Verilog HDL Function A.1.11.6. ebfm_log_close Verilog HDL Function
A.1.12. Verilog HDL Formatting Functions x
A.1.12.1. himage1 A.1.12.2. himage2 A.1.12.3. himage4 A.1.12.4. himage8 A.1.12.5. himage16 A.1.12.6. dimage1 A.1.12.7. dimage2 A.1.12.8. dimage3 A.1.12.9. dimage4 A.1.12.10. dimage5 A.1.12.11. dimage6 A.1.12.12. dimage7
1. About the GTS AXI Streaming IP for PCI Express* Design Example
2. Quick Start Guide
3. Document Revision History for the GTS AXI Streaming IP for PCI Express* Design Example User Guide
A. Appendix

2.2. Generating the Design Example

Figure 11. Procedure to Generate Design Example
  1. In the Quartus® Prime Pro Edition software, create a new project (File ➤ New Project Wizard). Click Next.
  2. Select Empty project type and specify the Directory, Name and Top-Level Entity. Click Next.
  3. For Family, Device & Board Settings under Family, select Agilex 3 or Agilex 5, and then select Target Device for your design. After that, click Finish to proceed.
  4. Select Tools → IP Catalog to open the IP Catalog. Then, select GTS AXI Streaming IP for PCI Express (Library → Interface Protocols → PCI Express → GTS AXI Streaming IP for PCI Express), and then click Add.
  5. In the New IP Variant dialogue box, specify a top-level name for your new custom IP variant and the directory for it. The IP Parameter Editor saves the IP variant settings in a file named <your_ip>.ip.
  6. Click Create. The GTS AXI Streaming IP for PCI Express IP Parameter Editor displays IP Settings, PCIe Settings, and Example Designs tabs to allow you to quickly configure your custom IP variant.
  7. On the System Settings tabs, specify the parameters for your IP variation.
  8. On the Example Designs tab, make the following selections:
    • For Example Design Files, turn on the Simulation and Synthesis options. If you do not need these simulation or synthesis files, leaving the corresponding option(s) turned off significantly reduces the design example generation time.
    • For Generated HDL Format, only Verilog is supported in the current release.
    • For Currently Selected Example Design, the PIO, SRIOV, and Performance design examples are supported in this release.
    • For Target Development Kit, select either the Agilex™ 5 FPGA E-Series 065B Modular Development Kit (ES1) (for the Agilex™ 5 device family only) or NONE to target the device selected for your current Quartus® Prime software project. When the Agilex™ 3 device is selected for the project, the Agilex™ 3 FPGA C-Series 135B Non-HPS Development Kit (Production) and NONE options are available instead. If you select the development kit, the settings including the pin assignments are included in the .qsf file of the generated design example, and you are not required to add them manually. These settings are board-specific for the development kit.
    Figure 12. Example Designs Tab
  9. Click Generate Example Design to generate the design example variant. When the prompt asks you to specify the directory for your design example, you can accept the default directory, /pcie_gts_0_example_design, or choose another directory. Then, click OK to kick off the design example generation.
  10. Click Finish. You may save your .ip file when prompted, but it is not required to be able to use the design example.
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