R-Tile PCIe* Hard IP

R-tile is a FPGA companion tile that supports PCIe* configurations up to 5 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer Packet (TLP) Bypass modes. PCIe 3.0, 4.0 and 5.0 configurations are natively supported. R-tile also supports up to 16 SerDes channels through a PHY Interface for PCIe (PIPE) 5.1.1 in SerDes Architecture mode.

R-tile serves as a companion tile for the Intel® Agilex™ I-series devices.

R-tile Avalon® Streaming Intel® FPGA IP for PCIe user guide ›

R-tile Avalon® Streaming Intel® FPGA IP for PCIe Design Example user guide

R-Tile PCIe* Hard IP

IP Quality Metrics

Basics

Year IP was first released

2021

Status

Preliminary

Deliverables

Customer deliverables include the following:

Design file (encrypted source code or post-synthesis netlist)

Timing and/or layout constraints

User guide

 

Y

Y

Y

Any additional customer deliverables provided with IP

Testbench, debug toolkit, and design examples

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

Verilog

Software drivers provided

Y

Driver OS Support

Linux

Implementation

User interface

Avalon Streaming, Avalon Memory-Mapped

IP-XACT metadata

N

Verification

Simulators supported

QuestaSIM, VCS

Hardware validated

Intel Agilex I-series

Industry standard compliance testing performed

Y

If Yes, which test(s)?

PCI-SIG

If Yes, on which Intel FPGA device(s)?

Intel Agilex I-series

If Yes, date performed

April 2022

If No, is it planned?

 

Interoperability

IP has undergone interoperability testing

N

If yes, on which Intel FPGA device(s)

 

Interoperability reports available

Y