R-Tile PCIe* Hard IP
R-Tile is a FPGA companion tile that supports configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass modes. PCIe 3.0, 4.0, and 5.0 configurations are natively supported. R-Tile also supports up to 16 SerDes channels through a PHY Interface for PCIe (PIPE) 5.1.1 in SerDes Architecture mode.
R-Tile PCIe* Hard IP
Companion Tile in Agilex™ 7 FPGA I-Series and M-Series Devices
- Available as hard IP (HIP) on R-Tile
- Full protocol stack implemented as hard IP with capability to bypass Transaction Layer
- Full PCIe 5.0 x16 performance and PCI-SIG compliant IP Core
- Blending both hard IP and soft IP for PCI Express provides the utmost flexibility, performance, and productivity
Standards and Specifications Compliance
- PCIe 5.0 Base Spec. Rev. 5.0, 1.0
- PIPE Serdes (SerDes-mode) Spec. 5.1
- R-tile PCIe Hard IP has passed PCI-SIG Compliance testing at the April'22 workshop. Refer to PCI-SIG Integrators List
Features
- Includes a complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as Hard IP
- PIPE mode support
- Natively supports PCIe 5.0/4.0/3.0 configurations with 2.0/1.0 configurations support via link down-training
- Supports Root Port and Endpoint modes
- Support for TL-Bypass mode to enable either UP-port or Down-port functionality for working with fabric-based PCIe Switch IP
- Various multilink EP, RP modes in lower width x4, x8 configurations available
- Multiple Bifurcation options
- Single Virtual Channel support
- Up to 512-byte Maximum Payload Size (MPS)
- Up to 4096-byte (4 KB) Maximum Read Request Size (MRRS)
- Support for various clocking modes: Common Reference Clock (refclk), Independent Reference Clock (refclk) with and without Spread Spectrum (SRIS, SRNS)
- Advanced Error Reporting
- Precision Time Management (PTM)
- Supports D0 and D3 PCIe power states
- Supports autonomous Hard IP mode that allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into user mode are complete
- FPGA core Configuration via PCIe link (CVP Init and CVP Update) and Partial Reconfiguration (PR) over PCIe link
Multifunction and Virtualization Features
- SR-IOV support (8 PFs, 2K VFs per each Endpoint)
- VirtIO support via configuration intercept interface
- Scalable I/O and Shared Virtual Memory (SVM) support
- Access Control Service (ACS)
- Alternative Routing-ID Interpretation (ARI)
- Function Level Reset (FLR)
- Support for TLP Processing Hint (TPH)
- Address Translation Services (ATS)
- Process Address Space ID (PasID)
User Interface Features
- Avalon® Streaming Interface (Avalon-ST)
- User packet interface with separate header, data, and prefix
- Quad segmented user packet interface with the ability to handle up to four TLPs in any given cycle (x16 core only)
- Extended Tag Support
- 10-bit Tag Support (maximum of 768 outstanding tags (x16) / 512 outstanding tags (x4/x8) at any given time, for all functions combined)
IP Debug Features
- Debug toolkit features:
- Protocol and link status information
- Basic and advanced debugging capabilities including PMA register access and Eye Viewing capability
Driver Support
- Linux device drivers
Boards and Kits
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