R-Tile PCIe* Hard IP

R-tile is a FPGA companion tile that supports PCIe* configurations up to 5 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer Packet (TLP) Bypass modes. PCIe 3.0, 4.0 and 5.0 configurations are natively supported. R-tile also supports up to 16 SerDes channels through a PHY Interface for PCIe (PIPE) 5.1.1 in SerDes Architecture mode.

R-tile serves as a companion tile for the Intel® Agilex™ I-series devices.

R-tile Avalon® Streaming Intel® FPGA IP for PCIe user guide ›

R-tile Avalon® Streaming Intel® FPGA IP for PCIe Design Example user guide ›

R-Tile PCIe* Hard IP

Standards & Specifications Compliance

  • PCIe 5.0 Base Spec. Rev. 5.0, 1.0
  • PIPE Serdes (SerDes-mode) Spec. 5.1
  • R-tile PCIe Hard IP has passed PCI-SIG Compliance testing at the April'22 workshop. Refer to PCI-SIG Integrators List.

Features

  • Includes a complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as a Hard IP.
  • Support for PIPE mode
  • Natively supports PCIe* 3.0/4.0/5.0 configurations with 1.0/2.0 configurations support via link down-training.
  • Supports Root Port (RP) and Endpoint (EP) modes.
  • Support for TL-Bypass mode to enable either UP-port or Down-port functionality for working with fabric-based PCI Switch IP.
  • Supports various multilink EP, RP modes in lower width x8, x4 configurations
  • Single Virtual Channel support
  • Supports up to 512-byte maximum payload size (MPS).
  • Supports up to 4096-byte (4 KB) maximum read request size (MRRS).
  • Support for various clocking modes: Common Reflect, Independent Refclks with & without Spread spectrum (SRIS, SRNS)
  • PCIe* Advanced Error Reporting
  • Supports D0 and D3 PCIe power states.
  • Supports autonomous Hard IP mode that allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into user mode are complete.
  • FPGA core configuration via PCIe link (CVP Init and CVP Update).

Multifunction and Virtualization Features

  • SR-IOV support (8 PFs, 2K VFs per each Endpoint)
  • VirtIO support via configuration intercept interface
  • Scalable I/O and shared virtual memory (SVM) support (future)
  • Access control service (ACS)
  • Alternative routing-ID interpretation (ARI)
  • Function level reset (FLR)
  • Support for TLP processing hint (TPH)
  • Suppot for Address Translation Services (ATS)
  • Process address space ID (PasID)

User Interface Features

  • Avalon® streaming interface (Avalon-ST) 
  • User packet interface with separate header, data and prefix.
  • Quad segmented user packet interface with the ability to handle up to four TLPs in any given cycle (x16 core only).
  • Extended Tag Support.
  • 10-bit Tag Support (Maximum of 768 outstanding tags (x16) / 512 outstanding tags (x8/x4) at any given time, for all functions combined).

IP Debug Features

  • Debug toolkit including the following features:
  • Protocol and link status information.
  • Basic and advanced debugging capabilities including PMA register access and Eye viewing capability.

Driver Support

  • Linux device drivers

IP Quality Metrics

Basics

Year IP was first released

2021

Status

Preliminary

Deliverables

Customer deliverables include the following:

Design file (encrypted source code or post-synthesis netlist)

Timing and/or layout constraints

User guide

 

Y

Y

Y

Any additional customer deliverables provided with IP

Testbench, debug toolkit, and design examples

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

Verilog

Software drivers provided

Y

Driver OS Support

Linux

Implementation

User interface

Avalon Streaming, Avalon Memory-Mapped

IP-XACT metadata

N

Verification

Simulators supported

QuestaSIM, VCS

Hardware validated

Intel Agilex I-series

Industry standard compliance testing performed

Y

If Yes, which test(s)?

PCI-SIG

If Yes, on which Intel FPGA device(s)?

Intel Agilex I-series

If Yes, date performed

April 2022

If No, is it planned?

 

Interoperability

IP has undergone interoperability testing

N

If yes, on which Intel FPGA device(s)

 

Interoperability reports available

Y
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