Scalable Switch Intel® FPGA IP for PCI Express
The Scalable Switch Intel® FPGA IP for PCI Express is a fully configurable switch that implements one fully configurable upstream port and connectivity for up to 32 downstream ports.
Read the Scalable Switch Intel® FPGA IP for PCI Express overview ›
Scalable Switch Intel® FPGA IP for PCI Express
Features
- Configurations
- 3.0 x4/x8/x16
- 4.0 x4/x8/x16
- Single physical function (PF)
Switch Logic
- Supports up to 32 downstream ports
Switch Downstream Port
- Single PF per downstream port
- Static device number allocation
- Supports Alternative Routing ID (ARI) forwarding for Discrete Ports
- Message Signaled Interrupts (MSI)
- Access Control Service (ACS) capability
- Capability only (no control functionality)
- Hot Plug support
- Configurations supported:
- 3.0 x4/x8/x16
- 4.0 x4/x8/x16
Embedded Endpoint
- Up to 32 embedded endpoint devices (one embedded endpoint behind each switch downstream port)
- MSI/MSI-X interrupts
- Elastic PF configuration, which is the capability to update the configuration space at any time
- ACS capability
- Capability only (no control functionality)
- Up to 8 PFs per embedded endpoint
- Maximum 32 PFs across all embedded endpoints
- Function Level Reset (FLR)
IP
- Support for P-Tile based devices: Intel® Stratix® 10 DX FPGAs and SoCs or selected members of the Intel Agilex® 7 FPGAs and SoC FPGAs F-series
- Optimized gate count
- User packet interface with separate header, data and prefix
- User packet interface provides one TLP in any given cycle for all configurations
- Up to 512 outstanding Non-Posted requests (x16 core only)
- Up to 256 outstanding Non-Posted requests (x8 and x4 cores)
- Device-dependent PLD clock (coreclkout_hip) frequency
- 400 MHz for Intel® Stratix® 10 DX devices, 500 MHz for Intel Agilex® 7 devices
Related Links
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