PCIe* Scalable Switch IP

The Intel Scalable Switch (soft) IP for PCIe is a fully configurable switch that implements one fully configurable upstream port and connectivity for up to 32 downstream ports.

Read the PCIe Scalable Switch Intel® FPGA IP user guide ›

PCIe* Scalable Switch IP

IP Quality Metrics

Basics

Year IP was first released

2020

Status

Production

Deliverables

Customer deliverables include the following:

Design file (encrypted source code or post-synthesis netlist)

Timing and/or layout constraints

Documentation with revision control

Yes for all below

Any additional customer deliverables provided with IP

Testbench & example design for a fixed Switch Configuration (1 UP port & 4 DN ports)

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

N

Source language

Verilog

Testbench language

Verilog

Software drivers provided

N/A

Driver OS Support

N/A

Implementation

User interface

Avalon Streaming (AVST)

IP-XACT metadata

Y

Verification

Simulators supported

VCS

Hardware validated

Intel Stratix 10 DX FPGA development kit

Industry standard compliance testing performed

N/A

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

N

If yes, on which Intel FPGA device(s)

N/A

Interoperability reports available

N/A