P-Tile PCIe* Hard IP

P-Tile is an FPGA Companion tile chiplet available on Intel® Stratix® 10 DX and Intel Agilex® 7 FPGA F-series device that natively supports PCIe for 4.0/3.0 functionality in Endpoint, Root Port, and TLP Bypass modes.

P-Tile Avalon® Streaming Intel® FPGA IP for PCIe user guide ›

P-Tile Avalon® Streaming Intel® FPGA IP for PCIe design example user guide ›

P-Tile PCIe* Hard IP

P-Tile Link Up Video

Watch the demo of Intel® Stratix® 10 DX device featuring P-tiles link up with Intel® Xeon server.

Standards & Specifications Compliance

  • P-Tile PCIe Hard IP successfully passed PCI-SIG Compliance testing. Results posted on the PCI-SIG integrators webpage.

PCIe* Features for P-Tile Hard IP

  • Complete protocol stack including the transaction, data link, and physical layers implemented as a Hard IP.
  • Natively supports up to 4x16 for endpoint and root port modes.
  • Port bifurcation capabilities: four x4s root port, two x8s endpoint.
  • Supports TLP bypass mode in both upstream and downstream modes.
  • Supports up to 512B maximum payload size (MPS).
  • Supports up to 4096-byte (4 KB) maximum read request size (MRRS).
  • Separate reference clock with independent spread spectrum Clocking (SRIS).
  • Separate reference clock with no spread spectrum clocking (SRNS)
  • Common reference clock architecture
  • Support for independent PERST to handle two reset operations (x8x8 EP and x8x8 TLP Bypass UP/UP).
  • PCIe advanced error reporting (PF only).
  • Support for D0 and D3 PCIe power states.
  • Lane margining at receiver
  • Retimers presence detection
  • Supports autonomous Hard IP mode that allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into user mode are complete.
  • FPGA core configuration via PCIe link (CVP Init and CVP Update).

Multifunction and Virtualization Features

  • SR-IOV support (8 PFs, 2K VFs per each Endpoint).
  • VirtIO support via configuration intercept interface.
  • Scalable I/O and shared virtual memory (SVM) support (future).
  • Access control service (ACS).
  • Alternative routing-ID interpretation (ARI).
  • Function level reset (FLR).
  • Suppot for TLP processing hint (TPH).
  • Support for Address Translation Services (ATS).
  • Process address space ID (PasID).

User Interface Features

  • Avalon® streaming interface (Avalon-ST).
  • User packet interface with separate header, data and prefix.
  • Dual segmented user packet interface with the ability to handle up to two TLPs in any given cycle (x16 core only).
  • Extended Tag Support
  • 10-bit Tag Support (Maximum of 768 outstanding tags (x16) / 512 outstanding tags (x8/x4) at any given time, for all functions combined).

Complementary IPs

IP Debug Features

  • Debug toolkit including the following features:
  • Protocol and link status information.
  • Basic and advanced debugging capabilities including PMA register access and Eye viewing capability.

Driver Support

  • Linux device drivers

IP Status

 

Ordering Status

No Ordering Code Required
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