P-Tile PCIe* Hard IP

P-Tile is an FPGA Companion tile chiplet available on Intel® Stratix® 10 DX and Intel® Agilex™ F-series device that natively supports PCIe for 4.0/3.0 functionality in Endpoint, Root Port, and TLP Bypass modes.

P-Tile Avalon® Streaming Intel® FPGA IP for PCIe user guide ›

P-Tile Avalon® Streaming Intel® FPGA IP for PCIe Design Example user guide ›

P-Tile PCIe* Hard IP

IP Quality Metrics

Basics

Year IP was first released

2019

Status

Production

Deliverables

Customer deliverables include the following:

Design file (encrypted source code or post-synthesis netlist)

Timing and/or layout constraints

Documentation with revision control

 

Y

Y

Y

Any additional customer deliverables provided with IP

Testbench and design examples

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

Verilog

Software drivers provided

Y

Driver OS Support

Linux

Implementation

User interface

Avalon streaming, Avalon memory mapped

IP-XACT metadata

N

Verification

Simulators supported

NCSim, ModelSim, VCS

Hardware validated

Intel Stratix 10 DX, Intel Agilex F-series

Industry standard compliance testing performed

Y

If Yes, which test(s)?

PCI-SIG

If Yes, on which Intel FPGA device(s)?

Intel Stratix 10 GX L-Tile, Intel Stratix 10 GX H-Tile, Intel Stratix 10 DX P-Tile

If Yes, date performed

Aug 2019 (Intel Stratix 10 FPGA P-Tile)

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

Y