L/H-tile PCIe* HARD IP

Intel® Stratix® 10 FPGAs incorporate the L/H-tile chiplets which include a configurable, hardened protocol stack for PCIe that is compliant with PCIe Base Specification 3.0. This Avalon® streaming interface Hard IP supports 1.0, 2.0 and 3.0 data rates and x1, x2, x4, x8, or x16 configurations, including support for SRIOV functionality.

Read the L- and H-Tile transceiver PHY user guide ›

Read the L- and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCIe user guide ›

Read the L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCIe user guide ›

L/H-tile PCIe* HARD IP

IP Quality Metrics

Basics

Year IP was first released

2016

Status

Production

Deliverables

Customer deliverables include the following:

    Design file (encrypted source code or post-synthesis netlist)

    Timing and/or layout constraints

    User guide

 

Y

Y

Y

Any additional customer deliverables provided with IP

Testbench and design examples

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

Verilog

Software drivers provided

Y

Driver OS Support

Linux

Implementation

User interface

Avalon Streaming, Avalon Memory-Mapped

IP-XACT metadata

N

Verification

Simulators supported

VCS, ModelSim* - Intel FPGA Edition

Hardware validated

Intel Stratix 10 GX

Industry standard compliance testing performed

Y

If Yes, which test(s)?

PCI-SIG

If Yes, on which Intel FPGA device(s)?

Intel Stratix 10 GX L-tile, H-tile

If Yes, date performed

December 2017

If No, is it planned?

N/A

Interoperability

IP has undergone interoperability testing

Y

If yes, on which Intel FPGA device(s)

Intel Stratix 10 GX L-tile, H-tile

Interoperability reports available

Y