F-Tile PCIe Hard IP
The F-Tile Intel® Hard IP supports PCIe* 4.0 in Endpoint, Root Port and TLP Bypass Modes. It also supports Avalon® streaming interfaces. F-tile serves as a companion tile for Intel Agilex® 7 devices.
F-Tile is the successor of P-Tile and natively supports PCIe 3.0 and 4.0 configurations.
Read the F-Tile Avalon® Streaming Intel® FPGA IP for PCIe user guide ›
Read the F-Tile Avalon® Streaming Intel® FPGA IP for PCIe design example user guide ›
F-Tile PCIe Hard IP
Standards & Specifications Compliance
- PCIe Base Specification Revision 4.0
- Single Root I/O Virtualization and Sharing Specification, Rev 1.1
- Address Translation Services, Revision 1.1
- PHY Interface for PCIe Architectures, Version 4.0
- Virtual I/O Device (VIRTIO) Version 1.0
Features
- Includes a complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as a Hard IP.
- Natively supports PCIe* 4.0/3.0 configurations with support for 1.0/2.0 configurations via link down-training.
- Supports Root Port (RP) and Endpoint (EP) modes.
- Support for TL-Bypass mode to enable either UP-port or Down-port functionality for working with fabric-based PCI Switch IP.
- Supports various multilink EP, RP modes in lower width x8, x4 configurations.
- Supports up to 512-byte maximum payload size (MPS).
- Supports up to 4096-byte (4 KB) maximum read request size (MRRS).
- Supports Single Virtual Channel (VC).
- Supports Completion Timeout Ranges through Completion Timeout Interface.
- Atomic Operations (FetchAdd/Swap/CAS).
- Support for various clocking modes: Common Reflect, Independent Refclks with & without Spread spectrum (SRIS, SRNS).
- PCIe* Advanced Error Reporting.
- ECRC generation and checking.
- Data bus parity protection.
- Supports D0 and D3 PCIe power states.
- Lane Margining at Receiver.
- Retimers presence detection.
- Supports autonomous Hard IP mode that allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into user mode are complete.
- FPGA core configuration via PCIe link (CVP Init and CVP Update).
Multifunction and Virtualization Features
- SR-IOV support (8 PFs, 2K VFs per each Endpoint).
- VirtIO support via configuration intercept interface.
- Scalable I/O and shared virtual memory (SVM) support (future).
- Access control service (ACS).
- Alternative routing-ID interpretation (ARI).
- Function level reset (FLR).
- Support for TLP processing hint (TPH).
- Support for Address Translation Services (ATS).
- Process address space ID (PasID).
User Interface Features
- Avalon® streaming interface (Avalon-ST)
- User packet interface with separate header, data and prefix.
- Dual segmented user packet interface with the ability to handle up to two TLPs in any given cycle (x16 core only).
- Extended Tag Support.
- 10-bit Tag Support (Maximum of 768 outstanding tags (x16) / 512 outstanding tags (x8/x4) at any given time, for all functions combined).
Complementary IPs
IP Debug Features
- Debug toolkit including the following features:
- Protocol and link status information.
- Basic and advanced debugging capabilities including PMA register access and Eye viewing capability.
Driver Support
- Linux device drivers.
Related Links
Documentation
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