F-Tile PCIe Hard IP

The F-Tile Intel® Hard IP supports PCIe* 4.0 in Endpoint, Root Port and TLP Bypass Modes. It also supports Avalon® streaming interfaces. F-tile serves as a companion tile for Intel® Agilex™ devices.

F-Tile is the successor of P-Tile and natively supports PCIe 3.0 and 4.0 configurations.

Read the F-Tile Avalon® Streaming Intel® FPGA IP for PCIe user guide ›

Read the F-Tile Avalon® Streaming Intel® FPGA IP for PCIe Design Example user guide ›

F-Tile PCIe Hard IP

IP Quality Metrics

Basics

Year IP was first released

2021

Status

Production

Deliverables

Customer deliverables include the following:

Design file (encrypted source code or post-synthesis netlist)

Timing and/or layout constraints

User guide

 

Y

Y

Y

Any additional customer deliverables provided with IP

Testbench and design examples

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel® FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

Verilog

Software drivers provided

Y

Driver OS Support

Linux

Implementation

User interface

Avalon streaming interface

IP-XACT metadata

N

Verification

Simulators supported

VCS

Hardware validated

Intel Agilex I-series

Industry standard compliance testing performed

N

If Yes, which test(s)?

 

If Yes, on which Intel FPGA device(s)?

 

If Yes, date performed

 

If No, is it planned?

Y

Interoperability

IP has undergone interoperability testing

N

If yes, on which Intel FPGA device(s)

 

Interoperability reports available

N