Signal Integrity and Power Integrity – Support Center
Intel is expanding the Intel® Agilex™ FPGA offering to include the new Intel® Agilex™ 9, 7, 5, and 3 FPGA product families.
The Signal Integrity and Power Integrity Support Center provides information on how to ensure signal integrity and power integrity in your high-speed designs.
Get support resources for Intel Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, and Knowledge Base.
Guidelines and Documentation
Board Design - General Guidelines
- Intel® Knowledge Data Base (KDB) for all FPGAs ›
- High-Speed Board Design Advisor ›
- Board Design Resource Center ›
- Input Signal Edge Rate Guidance White Paper ›
- Power Distribution Network (PDN) Checklist ›
- AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology ›
- AN 613: PCB Stackup Design Considerations for Intel® FPGAs ›
Board Design - External Memory Interfaces Guidelines
Board Design - Transceivers Guidelines
- UG-20298: Intel® Agilex™ Device Family High-Speed Serial Interface Signal Integrity Design Guidelines ›
- AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing ›
- AN 529: Via Optimization Techniques for High-Speed Channel Designs ›
- AN 530: Optimizing Impedance Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs ›
- AN 596: Modeling and Design Considerations for 10 Gbps Connectors ›
- AN 651: PCB Breakout Routing for High-Density Serial Channel Designs Beyond 10 Gbps ›
- AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission ›
- AN 678: High-Speed Link Tuning Using Signal Conditioning Circuitry in Stratix® V Transceivers ›
- AN 684: Design Guidelines for 100 Gbps - CFP2 Interface ›
- AN 689: High Speed Channel Design Using the SFF-8431 Protocol ›
- AN 766: Stratix 10 Devices, High Speed Signal Interface Layout Design Guideline ›
- Modeling Copper Surface Roughness for Multi-Gigabit Channel Designs ›
Training Videos
Title |
Type |
Description |
|---|---|---|
Online |
Learn about the need for accurate signal integrity simulation and analysis when designing high-speed PCBs using Intel FPGA transceivers. |
Additional Videos
Title |
Description |
|---|---|
Use the IBIS-AMI Model to Estimate Signal Integrity of Intel Arria 10 Transceiver |
Learn how to perform a signal integrity simulation with an Intel Arria 10 transceiver IBIS-AMI model in the Advanced Link Analyzer. Additionally, this video covers eye diagram reporting. |
Explore Other Developer Centers
For other design guidelines, visit the following Developer Centers:
- Board Developer Center - Contains detailed guidelines and considerations for high-speed PCB designs with Intel® FPGAs and SoC FPGAs.
- Embedded Software Developer Center - Contains guidance on how to design in an embedded environment with SoC FPGAs.
- FPGA Developer Center - Contains resources to complete your Intel® FPGA design.