AN 684: 100 Gbps CFP2 Design with Stratix V GT FPGAs

ID 683219
Date 1/16/2014

1. Design Guidelines for 100 Gbps - CFP2 Interface

This document shows an example layout design that implements a 4 x 25/28 Gbps CFP2 module interface that meets the insertion and return loss mask requirements proposed in the working clause draft version 8.0 for CEI-28G-VSR.

The common electrical interface CEI-28G-VSR implementation architecture (IA) for short reach channels is intended for next generation 100 Gbps chip - to - optical module applications. CFP2 is a pluggable optical module that uses CEI-28G-VSR as its electrical interface (as defined by the CFP Multi-Source Agreement (MSA) member companies). CFP2 also defines the mechanical form factor for a 100 Gbps optical transceiver module targeted for Ethernet and OTN (Optical Transport Network) applications.

CFP2 provides an industry standard to develop next generation 100 G interfaces with lower power and greater port density compared to previous generation CFP optical modules.

Note: For more information, refer to the CEI-28G-VSR working clause specification. Document number OIF2010.404.08.
Figure 1.  Stratix V GT Device to a CFP2 Pluggable Module Interface on a PCB

The channel layout on the PCB is optimized in order to meet the strict insertion and return loss masks defined by CEI-28G-VSR.

Refer to the following documents for more information on optimizing your board designs for high speed serial links.