AN 684: 100 Gbps CFP2 Design with Stratix V GT FPGAs

ID 683219
Date 1/16/2014

1.3. Stratix V GT to CFP2 Interface Layout Design

The TX and RX channels are connected directly to the CFP2 connector with approximately 5.5 inches of differential trace routing on the top and bottom layer of the board. DC blocking capacitors are included in the optical module for both the TX and RX traces. Nominal trace impedance is controlled at approximately 100Ω differential and the board material used is Panasonic Megtron-6.

Figure 6.  Stratix V GT to CFP2 Interface Layout Design Example The figure shows an example layout design where the green traces are the TX channels routed on the top layer while the orange traces are the RX channels routed on the bottom layer.

In this example, vias are used for the RX channel breakout at the BGA, and for both the TX and RX channels at the CFP2 connector. To avoid the top layer keep out requirement of the CFP2 metal connector cover assembly, the TX channel routing is switched briefly to the bottom layer and then back to the top layer at the CFP2 connector as illustrated by the circled area in the above figure. Top to bottom routing is used to avoid via stubs.

The BGA pads, signal vias, and CFP2 trace to pad interfaces are large discontinuity sources in the channel. Ansys HFSS (High Frequency Structural Simulator) 3-D field solver simulation is used to optimize the BGA breakout and CFP2 interface design. The trace impedance is kept within ±10% of the nominal 100Ω

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