AN 684: 100 Gbps CFP2 Design with Stratix V GT FPGAs

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ID 683219
Date 1/16/2014
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for 100 Gbps - CFP2 Interface
1. Design Guidelines for 100 Gbps - CFP2 Interface x
1.1. Stratix V GT Transceiver Channels 1.2. CFP2 Host Connector Assembly and Pinout 1.3. Stratix V GT to CFP2 Interface Layout Design 1.4. BGA Breakout Optimization 1.5. CFP2 Interface Optimization 1.6. Example Design Channel Performance 1.7. Document Revision History
1.3. Stratix V GT to CFP2 Interface Layout Design x
1.3.1. Board Stack Up Dimensions
1.6. Example Design Channel Performance x
1.6.1. Simulation Results for Stratix V GT to CFP2 Connector Layout Design
1. Design Guidelines for 100 Gbps - CFP2 Interface

1.6.1. Simulation Results for Stratix V GT to CFP2 Connector Layout Design

Ansys HFSS (High Frequency Structural Simulator) simulation results for the insertion loss (SDD21), return loss (SDD11) and differential-to-common mode conversion (SDC11) of the channel with the CFP2 connector included are shown in the following figures. The simulation models the HCB for validating the channel layout against the CEI-28G-VSR defined masks.

Figure 13.  Insertion Loss versus CEI-28G-VSR Mask Requirements

The SDD21 resides within the HCB minimum and maximum insertion loss masks as defined by the CEI-28G-VSR specification. This insertion loss meets the complete VSR channel (host board + connector + optical module) mask requirement with ample margin to accommodate the additional loss of an inserted CFP2 optical module. Note that the complete channel with the optical module is not simulated.



Similarly, the figures below show that the return loss and differential-to-common mode conversion both meet their respective masks as defined by the CEI-28G-VSR requirement.

Figure 14.  Return Loss versus CEI-28G-VSR Mask Requirements


Figure 15.  Mode Conversion versus CEI-28G-VSR Mask Requirements


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