AN 684: 100 Gbps CFP2 Design with Stratix V GT FPGAs

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ID 683219
Date 1/16/2014
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for 100 Gbps - CFP2 Interface
1. Design Guidelines for 100 Gbps - CFP2 Interface x
1.1. Stratix V GT Transceiver Channels 1.2. CFP2 Host Connector Assembly and Pinout 1.3. Stratix V GT to CFP2 Interface Layout Design 1.4. BGA Breakout Optimization 1.5. CFP2 Interface Optimization 1.6. Example Design Channel Performance 1.7. Document Revision History
1.3. Stratix V GT to CFP2 Interface Layout Design x
1.3.1. Board Stack Up Dimensions
1.6. Example Design Channel Performance x
1.6.1. Simulation Results for Stratix V GT to CFP2 Connector Layout Design
1. Design Guidelines for 100 Gbps - CFP2 Interface

1.6. Example Design Channel Performance

The CEI-28G-VSR working clause defines several mask requirements for the channel, including insertion loss, return loss, and differential-to-common mode conversion. Because it is difficult to verify electrical parameters of a full channel in a system, the working clause also defines a Host Compliance Board (HCB) with test points for verifying the host-to-module channel performance at various test points.

Figure 12.  Host Compliance Board Measurement Points


For example, TP1a and TP4a define the measurement points and the associated mask requirements for the host-to-module electrical signal performance for insertion loss, return loss, and differential-to-common mode conversion. For more information about these definitions, refer to the CEI-28G-VSR working clause specification (document number OIF2010.404.08).

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