Simultaneous Switching Outputs
As digital circuitry increases in speed, output-switching times decrease. Faster switching times cause higher transient currents within the outputs as the load capacitors discharge. If a number of outputs were to switch simultaneously from logic-high to logic-low, the charge will be stored in the I/O load capacitances to flow into the device. This sudden flow of current exits the device through internal inductances onto the board ground, causing a voltage to develop. This results in a voltage difference between the device and the board ground, momentarily developing a low voltage signal on the I/O above the ground level. This is known as "ground bounce". The bounce effect can cause an output-low to be seen as a high by other devices on the board.
Ground bounce can be reduced by following a number of board based design rules as outlined in AN 315: Guidelines for Designing High-Speed FPGA PCBs (PDF).
Altera® high-speed solutions provide pin slew rate control, which allows the designer to slow down the driver and therefore reduce the bounce effect. Additionally, the devices include multiple power and ground pins, thereby allowing the designer to locate a high-speed I/O pin close to a ground pin to reduce the effects of simultaneous switching outputs (SSO).
The challenges of high-speed design require some additional effort to ensure signal integrity. This can be achieved by following some simple analogue design rules and by using careful PCB layout techniques. Altera high-speed programmable logic devices provide many features to help support high-speed design, programmable slew rate control, and on-chip termination technology help to make designers’ work easier.