Signal Integrity Basics

Part I

Part II

Introduction

Traditionally, digital design was a relatively uncomplicated affair. Designers could develop circuitry operating up to 30 MHz without having to worry about issues associated with transmission line effects because, at lower frequency, the signals remained within data characterization, allowing the system to perform normally. As system performance increased, however, the designer’s challenges became more difficult—the impact of higher frequency on the system meant the designer had to consider not only the digital properties, but also the analogue effects within the system.

Some of the biggest design challenges surround the I/O signaling where transmission line effects can have a significant effect on the data being sent. At low speeds, the frequency response has little influence on the signal, unless the transmission medium is particularly long. However, as speed increases, high-frequency effects take over, and even the shortest lines can suffer from problems such as ringing, crosstalk, reflections and ground bounce, seriously hampering the response of the signal—thus damaging signal integrity. In reality, these problems can be overcome by good design technique and by following simple layout guidelines. Altera provides the information to help overcome these issues.

Transmission Line Effects

Transmission lines are connections capable of carrying a signal between a transmitter and a receiver. Traditionally, transmission lines have been considered to be telecom-based cables operating over long distances. But as digital signals are transmitted over high speed, even the shortest passive printed circuit board (PCB) track will suffer from transmission line effects.

At low frequencies, a wire or a PCB track may be an ideal circuit without resistance, capacitance or inductance. But at high frequencies, alternating (AC) circuit characteristics dominate causing impedances, inductances and capacitances to become prevalent in the wire. A circuit model can be calculated, as shown in figure 1 below, and used to determine the characteristic impedance of the wire or track. This impedance of the wire is extremely important, as any mismatch within the transmission path will result in a reduction in quality of the signal.

Figure 1. Circuit Model Representation of a Transmission Line

Impedance Mismatch

Impedance mismatch is caused when the output impedance of the source (ZS), the impedance of the line (ZO) and the impedance of the receiver or load (ZL) are not equal. This will mean the transmitted signal is not fully absorbed within the receiver and the excess energy will be reflected back to the transmitter. This process will continue back and forth until all of the energy is absorbed. At high data rates, this has dangerous effects on the signal, causing overshoot, undershoot, ringing, and stair-step waveforms, all of which produce errors in signaling.

When the transceiver buffers are matched to the transmission media, the impedance mismatch problem is solved. In the case of a PCB, this can be achieved by careful selection of medium and by the use of the proper termination schemes.

Figure 2. Simple Parallel Termination

A number of different termination methods are used to overcome this problem, depending on the application. These can include simple parallel termination on Stratix® GX devices (as shown in figure 2), and can range to more complex resistor capacitor (RC) termination, in which an RC network provides a low-pass filter to remove low frequency effects, but passes the high-frequency signal.

Although external components can often help the situation, they require PCB real estate and may also require additional track stubs, which can introduce new problems.

Altera® high-speed I/O solutions provide on-chip programmable termination to reduce the need of external components. Both Stratix and Stratix GX devices provide on-chip termination technology. This technology provides receiver- and transmitter-driver impedance matching for serial and differential I/O. The high-speed transceiver blocks on the Stratix GX devices additionally provide a programmable termination scheme within the high-speed transceiver circuitry to support most high-speed I/O standards. In addition to termination, good PCB design techniques can be used to overcome these issues.

Signal Attenuation

High-frequency signals are subject to losses along transmission lines, which interfere with the receiver’s ability to interpret the information. Table 1 lists some causes of the losses due to the transmission medium used to carry the signal.

Table 1. Causes of Losses Along Transmission Lines

Cause

Description

Dielectric Absorption

High-frequency signals excite molecules in the insulator causing it to absorb signal energy. This results in a reduction of the signal strength. Dielectric absorption is related to the printed circuit board (PCB) material being used, and can be improved by careful selection of material.

Skin Effect

Varying current waveforms, caused by AC and high-frequency signals, tend to travel on the surface of a conductor. This results in the self-inductance of the material producing an increased inductive reactance at high frequencies, forcing electrons to the surface of the material. The effective reduction of conductive area causes an increase of resistance and therefore attenuation of the signal. Increasing track width can reduce skin effect, but this is not always possible. Figure 3 illustrates this problem.

Careful selection of insulating material and track layout can help to overcome the issues of attenuation. Table 2 lists the circuitry in Stratix® GX Transceiver FPGAs that overcomes attenuation problems.

Table 2. Circuitry in Stratix GX Transceiver FPGAs to Overcome Attenuation Problems

Cause

Description

Pre-Emphasis

High-frequency attenuation cannot be achieved by boosting the signal strength alone, as this will also amplify noise and jitter associated with the signal. Pre-emphasis boosts only the high frequency components of the signal by increasing the level of the first transmitted symbol, while leaving the next symbols untouched—if they were transmitted at the same level.

For example, if a signal were to transmit a high level for three symbols, only the first symbol would be boosted, while the next two would be transmitted at the usual level. (See figure 3.) If a single symbol were transmitted at a high level, this would also be boosted.

Pre-emphasis is also a key function to overcome the effects of pattern-dependant jitter, including loss of amplitude, displacement in time, and rounded signal edges.

Receiver Equalization

Dedicated receiver circuitry is used to attenuate the high frequency components of the signal as it arrives at the receiver to compensate for line losses. Stratix GX devices have programmable equalization for 20” and 40” transmission lines.

Figure 3. Pre-Emphasis Over Two Unit Intervals

Cross-Talk

Whenever a signal is driven along a wire, a magnetic field is developed around that wire. If two wires are placed adjacent to each other, it is possible that the two magnetic fields will interact with the each other, causing a cross-coupling of energy between signals, known as cross-talk. Table 3 illustrates the types of coupling that exist which predominantly cause cross-talk.

Table 3. Types of Coupling That Cause Cross-Talk

Coupling

Description

Mutual Inductance

This is the effect of induced current from a driven wire, or aggressor, appearing on the quiet wire, or victim, by means of a magnetic field. Mutual inductance causes positive waves to appear on the near end of the victim line (closest to the transmitter) causing near-end inductance, while negative waves appear at the far end of the transmission line (nearer to the receiver), causing far-end cross-talk.

Mutual Capacitance

This is the coupling of two electric fields, where electrical current proportional to the rate of change of voltage in the driver is injected into the victim line. Mutual capacitance causes positive waves to appear at both ends of the transmission line.

Cross-talk can be significantly reduced by careful PCB design. The following steps describe how to reduce cross-talk in either micro-strip or strip-line layouts:

  • Widen spacing between signal lines as much as routing restrictions will allow
  • Design the transmission line so the conductor is as close to the ground plane as possible; this will couple the transmission line tightly to the ground plane and help decouple it from adjacent signals
  • Use differential routing techniques wherever possible, especially for critical PCB traces
  • Route signals on different layers, orthogonal to each other if there is significant coupling
  • Minimize parallel run lengths between signals; route with short parallel sections and minimize long coupled sections between nets

Simultaneous Switching Outputs

As digital circuitry increases in speed, output-switching times decrease. Faster switching times cause higher transient currents within the outputs as the load capacitors discharge. If a number of outputs were to switch simultaneously from logic-high to logic-low, the charge will be stored in the I/O load capacitances to flow into the device. This sudden flow of current exits the device through internal inductances onto the board ground, causing a voltage to develop. This results in a voltage difference between the device and the board ground, momentarily developing a low voltage signal on the I/O above the ground level. This is known as "ground bounce". The bounce effect can cause an output-low to be seen as a high by other devices on the board.

Ground bounce can be reduced by following a number of board based design rules as outlined in AN 315: Guidelines for Designing High-Speed FPGA PCBs (PDF).

Altera® high-speed solutions provide pin slew rate control, which allows the designer to slow down the driver and therefore reduce the bounce effect. Additionally, the devices include multiple power and ground pins, thereby allowing the designer to locate a high-speed I/O pin close to a ground pin to reduce the effects of simultaneous switching outputs (SSO).

The challenges of high-speed design require some additional effort to ensure signal integrity. This can be achieved by following some simple analogue design rules and by using careful PCB layout techniques. Altera high-speed programmable logic devices provide many features to help support high-speed design, programmable slew rate control, and on-chip termination technology help to make designers’ work easier.

Glosssary


0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z


0-98b10b
Method of encoding 8-bit data into a 10-bit form to ensure data is constructed of equal 1s and 0s. Used in high-speed clock data recovery (CDR) data transmissions to ensure data transition density, clock integrity, and DC balancing.
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AAlign Characters
Special code or comma transmitted to show start of data in a serial stream. Used by the receiver to re-align the data.
Attenuation
Reduction of signal amplitude that is commonly caused by the length a signal is required to travel.
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BBathtub Curve
Graphical representation of bit-error rate generated during bit-error rate testing. Shape often is similar to a bathtub due to the varying data edge placements used during the test.
BER
Bit-error rate. BER can be considered to be the number of bits of error divided by the number of bits received over a given time.
BERT
Bit-error rate tester. Instrument used to measure bit-error rate. Generally consists of a pattern generator and a signal analyzer.
BIST
Built-in self test. Circuitry built into the transceiver to allow testability without the need to connect to the outside world.
BW
Bandwidth. Frequency limits to which a system will perform.
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CCDR
Clock data recovery. A technique for embedding clock and data into a single signal for the sake of transmission. High-speed serial data require the clocks to be embedded into the data stream to remove skew and jitter issues associated with transmitting separately.
Channel Aligner
Transceiver circuitry used to align transceiver channels when more than one channel is required to handle a high-speed data interface.
CJTPAT
Continuous jitter pattern. IEEE test pattern used in 10-Gbit Ethernet compliance testing.
Code Groups
Selection of commas used in a particular protocol. For example XAUI utilizes /K/, /A/, /R/ & /T/ codes where /K/ indicates lane synchronization, /A/ indicates lane to lane alignment, /R/ indicates skip code, and /T/ indicates terminate.
Comma
Unique codes provided within 8b10b encoding for control information. Also known as K characters.
Common Mode (VCM)
A signal or noise of identical magnitude and phase that appears on both inputs of a differential receiver. This noise can then be removed at the input of the receiver, known as common mode rejection.
Compliance Points
Specific measurement points within a circuit. Used during system characterization to show that a signal conforms to specification.
Cross-Talk
Undesirable signal from one circuit superimposed onto a secondary circuit, caused by mutual inductance or mutual capacitance between the two circuits.
CRPAT
Continuous random pattern. IEEE test pattern used in 10-Gbit Ethernet compliance testing.
CRU
Clock recovery unit. Dedicated circuitry used to recover the clock within a CDR-based transmission scheme.
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DDC Balance
Stream of data encoded to ensure an equal balance of 1 or 0 . 8b10b encoding has been developed to ensure DC balancing.
DC Coupling
A method of coupling two different circuits together, allowing them to share both the static DC and varying AC characteristics of a signal.
DCD
Duty cycle distortion. Distortion in a waveform seen as a difference between the pulse width for a 1 and 0 signal. Also known as pulse width distortion.
DDJ
Data-dependant jitter. Jitter caused by pulse spreading due to system bandwidth limitation. Known as DDJ in time domain, or ISI in frequency domain.
Differential Signaling
Signaling scheme employing two complementary signals (equal and opposite) for every bit transmitted. Differential signaling allows any common noise to be removed by the buffer.
Discontinuities (Board Layout Context)
Poor layout of a PCB that causes the effect of an open track for high-speed signals resulting in signal reflection. Typical issues include placing vias at right angles or using 90° cornering during track layout.
DJ
Deterministic jitter. Reproducible jitter within a given system, under controlled conditions. Also known as bounded jitter.
DPA
Dynamic phase alignment. Method of aligning source-synchronous data to a transmitted clock, simplifying PCB layout by reducing skew issues. DPA can support data rates up to 1 Gbps for Stratix® GX devices.
DUT
Device under test. Describes the system or unit currently being tested.
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EEMI
Electromagnetic interference. Undesirable electromagnetic waves radiating from one circuit to another, causing interference or noise.
Equalization
Method of boosting the gain of a high-frequency signal to compensate for signal attenuation during transmission. Equalization circuitry is generally included within the receiver circuitry.
Eye Diagram
A superimposed high-speed waveform generated over a number of data cycles, depicting voltage and timing noise associated with a transmission line. The cleaner the eye within the plot, the better the signal.
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FFFT
Fast Fourier transform.
FR4
Standard laminate used in the construction of PCBs and backplanes.
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GGround Bounce
Momentary noise on the device ground plane causing a 0 signal to erroneously be seen as a 1. Ground bounce is caused by simultaneously switching outputs (SSO).
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HHSPICE
HP simulation program with integrated circuit emphasis. Analog circuit simulation models used to determine transceiver behavior during system simulation.
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IIBIS
I/O buffer information specification. I/O buffer behavioral models used to determine transceiver behavior during system simulation. IBIS models are not suitable for high-speed simulation above 1 Gbps.
Idle Characters
K (comma) code data sequence transmitted when data is not present, to maintain clock data synchronization. 8b10b encoding uses K28.5 code for this function.
Impedance Matching
Function of ensuring that the impedance of the transmitter, the receiver, and the transmission line are identical. Mismatched impedances could result in signal reflections, ringing, overshoot, undershoot, and stairstep waveforms.
ISI
Inter-symbol interference. Data corruption caused by residue of a previous signal interfering with the current data. Generally caused by reflections on the line.
ITU-T
International Telecommunications Union Telecommunication Standardization Sector. Telecommunication standards organization.
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JJBOD
Just a bunch of drives. Storage network term for a disk drive or number of disk drives mounted within their own enclosure but without any control processor.
Jitter
Time delay between the expected signal transition and the actual transition.
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LLAN
Local area network.
LDT
Lightning data transport. Low-voltage differential logic standard used within computer-based applications. Renamed to the HyperTransport™ standard.
LVDS
Low-voltage differential signaling. High-speed differential I/O interface commonly used in high-speed transceiver applications.
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MMitering (board layout context)
PCB term describing the layout technique used to ensure that high-speed I/O channels have an equivalent track length. Appear as wiggles on a PCB.
MJS
Methodologies for jitter specification. Document describing the jitter specification and measurements for a particular protocol that a product must reach before it conforms to the specification.
Mutual Capacitance
The coupling of two conductors via an electric field that injects a current onto the quiet line (victim) proportional to the rate of change of voltage on the driven line (aggressor).
Mutual Inductance
The effect of inducing current from a driven line (aggressor) onto a quiet line (victim) by means of an electric field.
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OOvershoot
The percentage a waveform rises above its upper determined value before setting at the correct value.
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P

PCB
Printed circuit board. Insulated sheet covered with a predefined pattern of conductive material, which becomes a circuit when populated with electronic components.
PCML
Positive emitter coupled logic. I/O standard based on emitter couple logic, used in high-speed applications due to its quick state switching properties.
PCS
Physical coding sub-layer. Many protocols divide the physical layer of the open system interconnection (OSI) model into two further sub-layers, PMA and PCS. The PCS sub-layer describes the digital functionality of the physical interface, including word alignment, pattern detection and data coding scheme such as 8b10b.
Pattern Detector
Transceiver logic used to identify specific data patterns within the data stream in order to align the data. Can use 8b10b comma codes, A1A2 patterns within SONET data, or user data codes.
PLL
Phase-locked loop. A closed-loop frequency-control system based on the phase difference between the input signal and the output signal of a controlled oscillator. PLLs can correct large and small frequency phase discrepancies through rough and fine tuning, respectively.
PMA
Physical medium attachment sub-layer. Many protocols divide the physical layer of the open system interconnection (OSI) model into two further sub-layers, PMA and PCS. The PMA sub-layer describes the analogue or electrical section of the interface.
PRBS
Pseudo random bit sequence. A telecommunication test sequence exhibiting certain qualities of randomness and autocorrelation. While a PRBS sequence can be used to evaluate a system's performance under random data conditions, it is fully predictable and repeatable.
Pre-Emphasis
Method of boosting a data signal to compensate for IR losses introduced by the transmission medium. Pre-emphasis boosts the initial signal when a transition occurs, but will de-emphasize a signal with a run length greater than 1 following the first unit interval.
PWD
Pulse width distortion (see DCD).
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RRate Matcher
Transceiver logic used to match received data to internal logic clock. In CDR-based systems, the clock frequencies of the transmitting and receiving devices often do not match. This mismatch can cause the data to transmit at a rate slightly faster or slower than the receiving device can interpret. The rate matcher resolves the frequency differences between the recovered clock and the PLD logic array clock by inserting or deleting removable characters from the data stream, as defined by the transmission protocol, without compromising transmitted data. Also known as clock correction.
Reflection
The appearance of a previously transmitted signal on the transmission line causing interference with the current signal. Reflections are caused by a poorly terminated or discontinuous transmission line, where the signal energy is not fully absorbed within the receiver and is therefore transmitted back towards the transmitter.
Ringing
The appearance of signal overshoot and undershoot at the receiver, caused by reflections on the transmission line.
RJ
Random jitter. Unpredictable jitter cased by random noise present during edge transitions, originating from poorly designed components or noisy power supplies.
RPAT
Random pattern. IEEE test pattern used in 10-Gbit Ethernet compliance testing.
Run Length
Number of unit intervals (UIs) before a transition must occur in order for the clock to be recovered from the data path. Refers to CDR-based transmissions.
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SScrambler
Pre-arranged transmission encoding scheme used to bit-disperse data in order to provide DC balancing and ensure CDR. Used in SONET/SDH applications.
SERDES
Serializer/ deserializer. Converts low-speed parallel data from source into high-speed serial data for transmission at the transmitter. Converts received high-speed serial data into low-speed parallel data at the receiver.
Signal Integrity
Design techniques used to ensure transmitted data can be successfully interpreted by the receiver within the tolerances of the protocol.
SJ (Sinusoidal Jitter)
Slow varying jitter, which is often tracked by a PLL. Sinusoidal jitter results from cross coupling of various signals within the system. Also known as cyclostationary noise.
Skew
Time delay between different bits transmitted at the same time, measured at the receiver.
Skip Characters
K (comma) characters used for data alignment. The receiver will remove these characters from a data stream to allow for skew issues between channels or between system clocks. Used for channel alignment and rate matching.
SONET
Synchronous optical network. Telecommunication network standard describing the connection of optical systems.
SSO
Simultaneous switching outputs. Condition where a number of outputs switch to the same level at the same time. This may result in ground bounce in a non-protected system.
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TTermination
Addition of passive components onto the transmission line to ensure impedance matching between transmitter, receiver, and transmission line.
TIA
Telecom Industry Association. Communication standards organization.
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UUndershoot
The percentage a waveform falls below its lowest determined value before setting at the correct value.
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VVia (PCB context)
Used as a method of interconnectivity for a multilayer PCB. Constructed using a tin plated hole connected to the tracks requiring connectivity.
VOD (VOD)
Voltage output differential. Describes the peak-to-peak voltage difference between an active low and active high signal voltage level.
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WWAN
Wide area network. A communications network used to connect a number of LANs together.
Wander
Similar to jitter. Long-term variation of a digital waveform from its original transmitted state.
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XXAUI
10-Gbit attachment unit interface. Describes optional 10-Gbps Ethernet connection between physical interface (PHY) and media access control (MAC). Can be used as an alternative to XGMII for chip-to-chip or backplane applications. XAUI provides a four-channel interface operating at 3.125 gigabits per second (Gbps).
XGMII
10-Gbit media independent interface. Describes 10-Gbps Ethernet interface connection between MAC and PHY. XGMII provides a 74-pin interface operating at 312 Mhz.
XSBI
10-Gbit sixteen-bit interface. Describes optional 10-Gbps Ethernet interface connection between MAC and PHY. Requires 16 differential lanes operating between 622 and 645 Mbps.
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