Intel® Quartus® Prime Design Software - Support Center
Welcome to the Intel® Quartus® Prime Design Software Support Center.
The Intel® Quartus® Prime Design Software Suite encompasses all software design tools needed to bring your Intel® FPGA from concept to production. The topics on this web page will guide you through all of the Intel® Quartus® Prime software features. Select your area of interest and navigate to the specific resources you need in the Intel® Quartus® Prime design flow.
- Intel® Quartus® Prime Software Quick Start Guide ›
- A brief guide on how to set up a project, compile, perform timing analysis, and program an FPGA device.
- Read Me First! (ORMF1000) ›
- A 47-minute free online course. This course is a starting point to quickly understand and use Intel® FPGA products, collateral, and resources.
Intel® Quartus® Prime Software User Guides
Intel® Quartus® Prime Pro Edition User Guides:
- Intel Quartus Prime Pro Edition User Guide: Getting Started ›
- Intel Quartus Prime Pro Edition User Guide: Platform Designer ›
- Intel Quartus Prime Pro Edition User Guide: Design Recommendations ›
- Intel Quartus Prime Pro Edition User Guide: Compiler ›
- Intel Quartus Prime Pro Edition User Guide: Design Optimization ›
- Intel Quartus Prime Pro Edition User Guide: Programmer ›
- Intel Quartus Prime Pro Edition User Guide: Block-Based Design ›
- Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration ›
- Intel Quartus Prime Pro Edition User Guide: Third-party Simulation ›
- Intel Quartus Prime Pro Edition User Guide: Third-party Synthesis ›
- Intel Quartus Prime Pro Edition User Guide: Debug Tools ›
- Intel Quartus Prime Pro Edition User Guide: Timing Analyzer ›
- Intel Quartus Prime Pro Edition User Guide: Power Analysis and Optimization ›
- Intel Quartus Prime Pro Edition User Guide: Design Constraints ›
- Intel Quartus Prime Pro Edition User Guide: PCB Design Tools ›
- Intel Quartus Prime Pro Edition User Guide: Scripting ›
Intel® Quartus® Prime Standard Edition User Guides:
- Intel Quartus Prime Standard Edition User Guide: Getting Started ›
- Intel Quartus Prime Standard Edition User Guide: Platform Designer ›
- Intel Quartus Prime Standard Edition User Guide: Design Recommendations ›
- Intel Quartus Prime Standard Edition User Guide: Compiler ›
- Intel Quartus Prime Standard Edition User Guide: Design Optimization ›
- Intel Quartus Prime Standard Edition User Guide: Programmer ›
- Intel Quartus Prime Standard Edition User Guide: Partial Reconfiguration ›
- Intel Quartus Prime Standard Edition User Guide: Third-party Simulation ›
- Intel Quartus Prime Standard Edition User Guide: Debug Tools ›
- Intel Quartus Prime Standard Edition User Guide: Third-party Synthesis ›
- Intel Quartus Prime Standard Edition User Guide: Timing Analyzer ›
- Intel Quartus Prime Standard Edition User Guide: Power Analysis and Optimization ›
- Intel Quartus Prime Standard Edition User Guide: Design Constraints ›
- Intel Quartus Prime Standard Edition User Guide: PCB Design Tools ›
- Intel Quartus Prime Standard Edition User Guide: Scripting ›
Intel® Quartus® Prime Software Training
Intel offers several types of training, both online and in-person to help get you up to speed quickly on the Intel® Quartus® Prime design flow. Here are some suggested training classes to get you started.
Intel® Quartus® Prime Software Training
|Course Name||Type||Duration||Course Number|
|Using the Quartus® Prime Software: An Introduction||Online||81 Minutes||ODSW1100|
|The Quartus® Prime Software: Foundation (Standard Edition)||Online||8 Hours||ODSW1110|
|The Quartus® Prime Software: Foundation (Pro Edition)||Online||8 Hours||ODSW1110PRO|
|Intel® Quartus® Prime Software: Pro Edition Features for High-End Designs||Instructor-Led / Virtual Class||8 Hours||IPRO|
|The Intel® Quartus® Prime Software: Foundation||Instructor-Led / Virtual Class||8 Hours||IDSW110|
1. I/O Planning
I/O Planning Overview
I/O planning is done at an early stage in FPGA design to ensure a successful placement in your target device while meeting dedicated pin and timing constraints. The Intel® Quartus® Prime Pro Edition software offers two tools to manage the complex process of meeting the many constraints of I/O placement.
Interface Planner manages the complexity of integrating multiple modules with hard requirements for pin assignments (for example, PCI Express*, DDR, and phase-locked loop (PLL) intellectual property (IP) cores). The Interface Planner interacts dynamically with the Intel® Quartus® Prime Fitter to verify placement legality while you plan. You can evaluate different floorplans using interactive reports to accurately plan the best implementation.
Pin Planner is a low-level pin assignment tool. Use this to manually place I/O pins and to specify slew rate and drive strength.
I/O Planning - Documentation and Training
I/O Planning - Software Tool Documentation
- Managing Device I/O Pins chapter in a section of the Intel® Quartus® Prime Pro Edition User Guide ›
- Interface Planning chapter in a section of the Intel® Quartus® Prime Pro Edition User Guide ›
I/O Planning - Device Documentation
I/O Planning - Training Classes
I/O Planning - Other Resources
I/O planning involves many considerations especially when high-speed I/Os or specific protocols are involved. For more information on I/O management and board development support, visit the I/O Management, Board Development Support, and Signal Integrity Analysis Resource Center web page.
2. Design Entry
Design Entry - Overview
You can express your design using several design entry methods:
- Using a hardware description language (HDL)
- Platform Designer, a graphical entry tool for connecting complex modules in a structured way
- Other high-level entry methods
- High Level Synthesis (HLS) using C++ to express complex modules
- OpenCL™ uses C++ to implement computational algorithms across heterogeneous platforms
In addition to direct design entry, Intel® FPGAs support a large portfolio of intellectual property (IP) designed specifically for use in Intel® FPGAs.
Learning a Hardware Description Language (HDL)
Intel offers several HDL training courses, from free online overviews to full day-long instructor-led classes.
|Introduction to Verilog HDL||8 Hours||Instructor-Led||IHDL120|
|Introduction to VHDL||8 Hours||Instructor-Led||IHDL110|
|Verilog HDL Basics||50 Minutes||Online, Free||OHDL1120|
|VHDL Basics||92 Minutes||Online, Free||OHDL1110|
|Advanced Verilog HDL Design Techniques||8 Hours||Instructor-Led||IHDL230|
|Advanced VHDL Design Techniques||8 Hours||Instructor-Led||IHDL240|
|SystemVerilog with the Quartus® II Software||38 Minutes||Online, Free||OHDL1125|
Using HDL Templates
The Intel® Quartus® Prime software offers several templates for commonly used logic elements such as registers, selected signal assignments, concurrent signal assignments, and subprogram calls. Templates are available in Verilog, SystemVerilog, and VHDL.
If you are unsure of the best way to write a specific function to ensure that it will be implemented correctly, you should refer to these templates. The template system is fully described in the Inserting HDL Code from a Provided Template section in the Design Recommendations User Guide.
Recommended HDL Coding Style
HDL coding styles have a significant effect on the quality of results for logic designs. Synthesis tools will optimize the design, but to achieve precise results, you need to code in a style, which will be readily recognized by the synthesis tool as specific logic constructs.
In addition, there are good design practices, which should be followed for general digital logic design and for LAB-based devices in particular. Managing logic reset methodologies, pipeline delays, and proper synchronous signal generation are some examples of good digital design practices. Some resources for learning good HDL coding practices are listed below.
Resources for Good HDL Coding Style Guidelines
|Good High-Speed Design Practices (ODSWTC01)||Free, online training|
|Recommended HDL Coding Styles||A section in the Intel® Quartus® Prime Pro Edition User Guide|
|Recommended Design Practices||A section in the Intel® Quartus® Prime Pro Edition User Guide|
|Advanced Synthesis Cookbook with design examples (cookbook.zip)||PDF with design examples|
Intel® FPGAs support a large portfolio of intellectual property (IP) designed specifically for use in Intel® FPGAs. Each IP includes a simulation model for design verification before device implementation. See the following links for more information on available IP cores and the IP ecosystem within the Intel® Quartus® Prime software.
Intellectual Property Resources
Platform Designer Documentation
|Creating a System with Platform Designer||Basics of using the Platform Designer|
|Creating Platform Designer Components||How to integrate intellectual property (IP) components for use in the Platform Designer|
|Platform Designer Interconnect||Details on the memory-mapped and streaming interfaces available in the Avalon® and AMBA* AXI* interconnection standards|
|Optimizing Platform Designer System Performance||Optimizing pipelines and dealing with bus arbitration in a Platform Designer system|
|Component Interface Tcl Reference||Application programming interface (API) reference for integrating IP into the Platform Designer system|
|Platform Designer System Design Components||Description of the interconnection components available in the Platform Designer|
Platform Designer (formerly Qsys) Training Courses
|Creating a System Design with Qsys||37 Minutes||Free, Online||OQSYSCREATE|
|Introduction to Qsys||26 Minutes||Free, Online||OQSYS1000|
|Introduction to the Platform Designer System Integration Tool||8 Hours||Instructor-Led||IQSYS101|
|System Design with Qsys Pro||42 Minutes||Free, Online||OQSYSPRO|
|Advanced System Design Using Qsys: Component & System Simulation||28 Minutes||Free, Online||OAQSYSSIM|
|Advanced System Design Using Qsys: Qsys System Optimization||32 Minutes||Free, Online||OAQSYSOPT|
|Advanced System Design Using Qsys: System Verification with System Console||25 Minutes||Free, Online||OAQSYSSYSCON|
|Advanced System Design Using Qsys: Utilizing Hierarchy in Qsys Designs||22 Minutes||Free, Online||OAQSYSHIER|
|Advanced Qsys System Integration Tool Methodologies||8 Hours||Instructor-Led||IQSYS102|
|Custom IP Development Using Avalon® and AXI* Interfaces||113 Minutes||Free, Online||OQSYS3000|
Platform Designer Design Examples
|Platform Designer - Design Example||Downloadable design example of a memory tester implemented in the Platform Designer.|
|AXI* Memory Design Example||AMBA* AXI*-3 Agent interface on a simple Verilog custom memory component.|
|BFM Simulation Example: HPS AXI* Bridge Interface to FPGA Core||A hard processor system (HPS) interface to the FPGA AXI* bridge (h2f).|
|Avalon® Verification IP Suite User Guide (PDF)||Bus functional models (BFMs) to verify IP cores using Avalon® interfaces.|
|Design files (.zip)|
|Mentor Graphics* AXI* Verification IP Suite (PDF)||BFMs to verify IP cores using AMBA* AXI* interfaces.|
|Comparing IP Integration Approaches for FPGA Implementation||Discusses the interconnection challenges in complex FPGA devices.|
|Applying the Benefits of Network on a Chip Architecture to FPGA System Design||Describes the advantages of network on a chip (NoC) architectures in Intel® FPGA system design.|
The Intel® Quartus® Prime software supports RTL and gate-level design simulation in supported EDA simulators.
- Setting up your simulator working environment
- Compiling simulation model libraries
- Running your simulation
The Intel® Quartus® Prime software supports the use of a scripted simulation flow to automate simulation processing in your preferred simulation environment.
In the Intel® Quartus® Prime Standard Edition software, you have the option of using the NativeLink tool flow, which automates the launch of your chosen simulator.
Scripted Simulation Flow
The integration of an HDL simulator into the Intel® Quartus® software tool flow is described in the following section of the Intel® Quartus® software User Guide | Handbook:
When using the Platform Designer to configure IP cores and systems, simulation environment setup scripts are generated for supported EDA simulators.
When creating multiple Platform Designer systems, you should run "Generate Simulator Setup Script for IP" to create a combined script for your systems in the Platform Designer.
You can incorporate generated IP core simulation scripts into a top-level simulation script that controls the simulation of your entire design. After running ip-setup-simulation, use the following information to copy the template sections and modify them for use in a new top-level script file.
- Aldec Active-HDL ( Pro Edition | Standard Edition )
- Aldec Riviera-PRO ( Pro Edition | Standard Edition )
- Cadence Incisive Enterprise ( Pro Edition | Standard Edition )
- Mentor Graphics* ModelSim*-Intel® FPGA Edition (bundled with the Intel® Quartus® Prime software) ( Pro Edition | Standard Edition )
- Mentor Graphics* ModelSim* - PE ( Pro Edition | Standard Edition )
- Mentor Graphics* ModelSim* - SE ( Pro Edition | Standard Edition )
- Mentor Graphics* QuestaSim ( Pro Edition | Standard Edition )
- Synopsys* VCS and VCS MX ( Pro Edition | Standard Edition)
You can also refer to the following videos for guidance on setting up simulations.
NativeLink Simulation Flow
In the Intel® Quartus® Prime Standard Edition software, you have the option of using NativeLink. This lets you automatically launch all the steps needed to simulate your design after modifying your source code or IP.
The NativeLink feature integrates your EDA simulator with the Intel® Quartus® Prime Standard Edition software by automating the following:
- Generation of simulator-specific files and simulation scripts.
- Compilation of simulation libraries.
- Automatic launching of your simulator following the Intel® Quartus® Prime software analysis and elaboration, analysis and synthesis, or after a full compilation.
Resources for NativeLink Simulation Setup
The Intel® Quartus® Prime Standard Edition software supports these EDA Simulators:
- Aldec Active-HDL
- Aldec Riviera-PRO
- Cadence Incisive Enterprise
- Mentor Graphics* ModelSim*-Intel FPGA (bundled with the Intel® Quartus® Prime software)
- Mentor Graphics* ModelSim* - PE
- Mentor Graphics* ModelSim* - SE
- Mentor Graphics* QuestaSim
- Synopsys* VCS and VCS MX
The integration of an HDL simulator into the Intel® Quartus® software tool flow is described in the Simulating Intel FPGA Designs section in Intel Quartus Prime Pro Edition User Guide: Third-Party Simulation.
The Logic Synthesis stage of the Intel® Quartus® software design flow will take the register transfer level (RTL) code and create a netlist of lower level primitives (the post-synthesis netlist). The post-synthesis netlist will then be used as an input to the Fitter, which will place and route the design.
The Intel® Quartus® Prime and Quartus® II software include advanced integrated synthesis and interfaces with other third-party synthesis tools. The software also offers schematic netlist viewers that you can use to analyze a structure of a design and see how the software interpreted your design.
Synthesis results can be viewed with the Quartus® Netlist viewers, both after RTL elaboration and after Technology Mapping.
|Quartus Prime Integrated Synthesis||The Intel® Quartus® Prime software integrated synthesis tool supports the synthesis of VHDL, Verilog, SystemVerilog, and legacy Intel® FPGA-specific design entry languages.|
|Synplify Support||The Intel® Quartus® Prime software tool flow also supports the Synplicity Synplify and Synplify Pro logic synthesizers.|
|Mentor Graphics* Precision RTL Support||The Intel® Quartus® Prime software tool flow also supports the Mentor Graphics* Precision RTL Synthesizer.|
Synthesis Training and Demonstrations
|Using the Quartus® Prime Software: An Introduction (ODSW1100)||
Become familiar with the basic Quartus® Prime software design environment. You will learn about a basic FPGA design flow and how to use the Quartus® Prime software in the flow.
This is a 1.5-hour online course.
|The Quartus® Prime Software Design Series: Foundation (Standard) (ODSW1110)||
Learn to use the Quartus® Prime software to develop an FPGA or CPLD design from initial design to device programming.
This is a 3.5-hour online course.
|The Quartus® Prime Software Design Series: Foundation (IDSW110)||
Create a project, enter design files, compile, and configure your device to see the design working in-system. Enter timing constraints and analyze a design using the Timing Analyzer. Discover how the software interfaces with common EDA tools used for synthesis and simulation.
This is an 8-hour instructor-led course.
Intel's high-level synthesis (HLS) tool takes in a design description written in C++ and generates RTL code that is optimized for Intel® FPGAs.
For more information on the Intel® HLS Compiler, including documentation, examples, and training courses, view the HLS Support Page.
|HLS Getting Started Guide||Shows how to initialize your high-level synthesis compiler environment. Also includes design examples and tutorials to demonstrate ways to effectively use the compiler.|
|HLS User Guide||Provides instructions on synthesizing, verifying, and simulating IP cores for Intel® FPGA products.|
|HLS Reference Manual||Provides information about the high-level synthesis (HLS) component design flow, including command options and other programming elements you can use in your component code.|
|HLS Best Practices Guide||Offers tips and guidance on how to optimize your component design using information provided by the HLS compiler.|
Fitter - Pro Edition
With the Intel® Quartus® Prime Pro Edition software, the Fitter does its work in individually controllable stages; you can optimize each stage individually by running just that stage of the fitter process, iterating to optimize that stage.
|Fitter Stage||Incremental Optimization|
|Plan||After this stage, you can run post-plan timing analysis to verify timing constraints and validate cross-clock timing windows. View the placement and periphery properties and perform clock planning for Intel® Arria® 10 FPGA and Intel® Cyclone® 10 FPGA designs.|
|Early Place||After this stage, the Chip Planner can display an initial high-level placement of design elements. Use this information to guide your floorplanning decisions. For Intel® Stratix® 10 FPGA designs, you can also do early clock planning after running this stage.|
|Place||After this stage, validate the resource and logic utilization in the Compilation Reports and review the placement of design elements in the Chip Planner.|
|Route||After this stage, perform detailed setup and hold timing closure in the Timing Analyzer and view routing congestions via the Chip Planner.|
|Retime||After this stage, review the Retiming results in the Fitter report and correct any restrictions limiting further retiming optimization.|
By default, the Fitter will run through all its stages. However, you can analyze the results of Fitter stages to evaluate your design before running the next stage, or before running a full compilation. For more information on how to use the Fitter stages to control the quality of results for your design, refer to the Running the Fitter section in the Compiler User Guide: Intel® Quartus® Prime Pro Edition.
You can specify several settings to direct the effort level of the Fitter for such things as register packing, register duplication and merging, and overall effort level. For more information on Fitter settings, see discussions under the Fitter Settings Reference section in the Compiler User Guide: Intel® Quartus® Prime Pro Edition.
Fitter - Standard Edition
In the Intel® Quartus® Prime Standard Edition software, you can specify several settings to direct the effort level of the Fitter such as register packing, register duplication and merging, and overall effort level. For a complete listing of Fitter Settings, see Compiler Settings Help Page
For more information on Fitter settings, see discussions under
6. Timing Analysis
Timing Analysis Overview
The Timing Analyzer determines the timing relationships that must be met for the design to correctly function and checks arrival times against required times to verify timing.
Timing analysis involves many foundational concepts: asynchronous v. synchronous arcs, arrival and required times, setup and hold requirements, etc. These are defined in the Timing Analysis Basic Concepts section of the Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer.
The Timing Analyzer applies your timing constraints and determines timing delays from the results of the Fitter's implementation of your design into the target device.
The Timing Analyzer must operate from an accurate description of your timing requirements, expressed as timing constraints. The Constraining Designs section of the Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer describes how timing constraints can be added to.sdc files, for use by both the Fitter and the Timing Analyzer.
Timing closure is an iterative process of refining timing constraints; adjusting parameters for synthesis and the Fitter, and managing fitter seed variations.
The Intel Quartus Prime Timing Analyzer
The Timing Analyzer in the Intel® Quartus® Prime software is a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industry standard constraint, analysis, and reporting methodology. The Timing Analyzer can be driven from a graphical user interface or from a command-line interface to constrain, analyze, and report results for all the timing paths in your design.
A full user guide on the Timing Analyzer can be found in the Running the Timing Analyzer section of the Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer.
If you are new to Timing Analysis, see the Recommended Flow for First Time Users section of the Intel® Quartus® Prime Standard Edition User Guide: Timing Analyzer. This describes the full design flow using basic constraints.
Timing Analyzer Training Courses
|The Intel Quartus Prime Software Design Series: Timing Analysis||8 Hours||Intructor-Led||IDSW120|
|Advanced Timing Analysis with TimeQuest||8 Hours||Instructor-Led||IDSW125|
|Timing Analyzer: Introduction to Timing Analysis||15 Minutes||Online, Free||ODSW1115|
|Timing Analyzer: Timing Analyzer GUI||31 Minutes||Online, Free||ODSW1116|
|Timing Analyzer: Intel Quartus Prime Integration & Reporting||25 Minutes||Online, Free||ODSW1117|
|Timing Analyzer: Required SDC Constraints||34 Minutes||Online, Free||ODSW1118|
|Timing Closure Using TimeQuest Custom Reporting||24 Minutes||Online, Free||OTIM1100|
If the Timing Analyzer determines that your timing specifications are not met, then the design must be optimized for timing until the discrepancy is closed and your timing specifications are met.
Timing closure involves several possible techniques. The most effective techniques will vary with each design. The Timing Closure and Optimization chapter in the Design Optimization User Guide: Intel Quartus Prime Pro Edition gives a lot of practical advice about the timing closure process.
There are several additional training courses to help you understand how to evaluate your design for the right timing closure techniques.
Timing Closure Training Courses
|Incremental Block-Based Compilation in the Intel® Quartus® Prime Pro Software: Timing Closure & Tips||22 Minutes||Online, Free||OIBBC102|
|Design Evaluation for Timing Closure||55 Minutes||Online, Free||ODSWTC02|
|Best HDL Design Practices for Timing Closure||61 Minutes||Online, Free||OHDL1130|
|Timing Closure Using TimeQuest Custom Reporting||24 Minutes||Online, Free||OTIM1100|
|Timing Closure with the Quartus® II Software||8 Hours||Instructor-Led||IDSW145|
7. Design Optimization
Design Optimization Overview
The Intel® Quartus® Prime and Quartus® II software include a wide range of features to help you optimize your design for area and timing. This section provides the resources to help you with design optimization techniques and tools.
The Intel® Quartus® Prime and Quartus® II software offer physical synthesis netlist optimization to optimize designs further than the standard compilation process. Physical synthesis helps improve the performance of your design, regardless of the synthesis tool used.
Optimization Support Documentation
|Area and Timing Optimization||This user guide section explains how to reduce resource usage, reduce compilation times, and improve timing performance when designing for Intel® devices.|
|Analyzing and Optimizing the Design Floorplan||This user guide section describes how to use the Chip Planner to analyze and optimize the floorplan for your designs. This chapter also explains how to use Logic Lock Region to control the placement.|
|Engineering Change Management with the Chip Planner||This user guide section describes how to use the Chip Planner to implement engineering change orders (ECOs) for supported devices.|
|Netlist Optimizations and Physical Synthesis||This user guide section explains how the netlist optimizations and physical synthesis in Intel® Quartus® Prime software can modify your design’s netlist and help improve the quality of your results.|
|Incremental Compilation Resource Center||This resource center web page shows how you can use incremental compilation to reduce compilation times and preserve results during optimization.|
Design Optimization Training Courses
|Using Intel® Quartus® Prime Pro Software: Chip Planner||29 Minutes||Online, Free||OPROCHIPPLAN|
|Using Design Space Explorer||21 Minutes||Online, Free||ODSE|
|Timing Closure Using Timequest Custom Reporting||24 Minutes||Online, Free||OTIM1100|
|Best HDL Design Practices for Timing Closure||1-hour||Online, Free||OHDL1130|
Design Optimization Tools
The Intel® Quartus® Prime software provides tools that present your design in visual ways. These tools let you diagnose any problem areas in your design, in terms of logical or physical inefficiencies.
- You can use the Netlist Viewers to see a schematic representation of your design at several stages in the implementation process: before synthesis, after synthesis, and after place-and-route. This enables you to confirm your design intent at each stage.
- The Design Partition Planner helps you visualize and revise a design's partitioning scheme by showing timing information, relative connectivity densities, and the physical placement of partitions. You can locate partitions in other viewers, or modify or delete partitions.
- With the Chip Planner, you can make floorplan assignments, perform power analysis, and visualize critical paths and routing congestion. The Design Partition Planner and the Chip Planner allow you to partition and layout your design at a higher level.
- Design Space Explorer II (DSE) automates the search for the settings that give the best results in any individual design. DSE explores the design space of your design, applies various optimization techniques, and analyzes the results to help you discover the best settings for your design.
Using these tools can help you optimize the implementation of the device.
The Intel® Quartus® Prime software netlist viewers provide powerful ways to view your design at various stages. Cross probing is possible with other design views: you can select an item and highlight it in the Chip Planner and Design File Viewer windows.
- The RTL Viewer shows the logic and connections inferred by the synthesizer, after elaboration of the hierarchy and major logic blocks. You can use the RTL Viewer to check your design visually before simulation or other verification processes.
- The Technology Map Viewer (Post-Mapping) can help you locate nodes in your netlist after synthesis but before place-and-route.
- The Technology Map Viewer (Post-Fitting) shows the netlist after place-and-route. This can differ from the Post-Mapping netlist because the fitter may make optimizations in order to meet constraints during physical optimization.
Netlist and Finite State Machine Viewers
See a demonstration of the Quartus® software Netlist Viewer and Finite State Machine Viewer in the videos below.
Netlist Viewers Resources
Design floorplan analysis helps to close timing and ensure optimal performance in highly complex designs. The Chip Planner in the Intel® Quartus® Prime software helps you close timing quickly on your designs. You can use the Chip Planner together with Logic Lock Regions to compile your designs hierarchically and assist with floorplanning. Additionally, use partitions to preserve placement and routing results from individual compilation runs.
You can perform design analysis as well as create and optimize the design floorplan with the Chip Planner. To make I/O assignments, use the Pin Planner.
Chip Planner Resources
|Analyzing and Optimizing the Design Floorplan||Design Optimization User Guide: Intel® Quartus® Prime Pro Edition Chapter||Primary documentation for Design Floorplan and Chip Planner|
|Chip Planner Instructional Video (Part 1 of 2)||E2E Video||Chip Planner tutorial: Cross Reference Timing Paths, Fan-in, Fan-out, Routing Delays, and Clock Regions|
|Chip Planner Instructional Video (Part 2 of 2)||E2E Video||Chip Planner tutorial: Routing Utilization, Design Element Search, and Logic Lock Regions|
|Making ECO changes using Intel FPGA Quartus Chip Planner and Resource Property Editor (Part 1 of 3)||E2E Video||Making late, small engineering change order (ECO) changes using the Chip Planner|
|Making ECO changes using Intel FPGA Quartus Chip Planner and Resource Property Editor (Part 2 of 3)||E2E Video||Making late, small ECO changes using the Chip Planner|
|Making ECO changes using Intel FPGA Quartus Chip Planner and Resource Property Editor (Part 3 of 3)||E2E Video||Making late, small ECO changes using the Chip Planner|
|How to trace the local routing of CDR recovered clock from transceiver channel to I/O pin using the Timing Analyzer and Chip Planner||E2E Video||An example of how to use the Chip Planner with the Timing Analyzer|
Design Space Explorer II
Design Space Explorer II (DSE) allows you to explore the many parameters available for design compilation.
You can use the DSE to manage multiple compilations with different parameters to find the best combination of parameters that allow you to achieve timing closure.
Design Space Explorer II Resources
8. On-Chip Debugging
On-Chip Debugging Overview
As FPGAs increase in performance, size, and complexity, the verification process can become a critical part of the FPGA design cycle. To alleviate the complexity of the verification process, Intel provides a portfolio of on-chip debugging tools. The on-chip debugging tools allow real-time capture of internal nodes in your design to help you verify your design quickly without the use of external equipment, such as a bench logic analyzer or protocol analyzer. This can alleviate the number of pins needed for board-level signal probing. For a guide to all the tools in the debug portfolio, refer to the System Debugging Tools section in the Debug Tools User Guide: Intel® Quartus® Prime Pro Edition.
- System Console - Using a Tcl interpreter, System Console presents a scriptable interface between a workstation and Platform Designer components on your device.
- Transceiver Toolkit - Test and tune transceiver link signal quality
- Signal Tap Logic Analyzer - Uses local FPGA resources to sample test nodes and outputs the information through graphical waveform displays in the Intel Quartus Prime software GUI
- Signal Probe - incrementally route internal signals to I/O pins for monitoring
- Logic Analyzer Interface - Multiplex a set of signals to a small number of spare I/O pins for monitoring
- In-System Sources and Probes - Drive and sample logic values using JTAG
- In-System Memory Content Editor - Display and edit on-chip memory
- Virtual JTAG Interface - Allow communications with the JTAG interface
External memory debugging is facilitated by the Extermal Memory Interface Toolkit, which is detailed in the External Memory Interface Support Center.
The Transceiver Toolkit offers extensive facilities to verify transceiver signal quality and performance. For more information on this toolkit, see the Transceiver Toolkit product page.
On-Chip Debugging Examples
On-Chip Debug Design Examples
Here are some examples to help you leverage the available features for common debug scenarios.
On-Chip Debugging - Training Courses
On-Chip Debugging Training Courses
|SignalTap II Logic Analyzer: Introduction & Getting Started||35 Minutes||Online, Free||ODSW1164|
|SignalTap II Logic Analyzer: Basic Trigger Conditions & Configuration||28 Minutes||Online, Free||ODSW1171|
|SignalTap II Logic Analyzer: Triggering Options, Compilation, & Device Programming||28 Minutes||Online, Free||ODSW1172|
|SignalTap II Logic Analyzer: Data Acquisition & Additional Features||30 Minutes||Online, Free||ODSW1173|
|The Quartus® Software Debug Tools||8 Hours||Instructor-Led||IDSW135|
|Debugging & Communicating with an FPGA Using the Virtual JTAG Megafunction||38 Minutes||Online, Free||OVJTAG1110|
|Debugging JTAG Chain Integrity||32 Minutes||Online, Free||ODJTAG1110|
|On-Chip Debugging of Memory Interfaces IP in Arria® 10 Devices||32 Minutes||Online, Free||OMEM1124|
|System Console||29 Minutes||Online, Free||OEMB1117|
|Advanced System Design Using Qsys: System Verification with System Console||25 Minutes||Online, Free||OAQSYSSYSCON|
On-Chip Debugging - Other Resources
On-chip Debug - other resources
|Intel® FPGA Virtual JTAG (Intel® FPGA_virtual_jtag) IP Core User Guide (PDF)||The Intel® FPGA_virtual_jtag Intel® FPGA IP communicates via a JTAG port, allowing you to develop custom debugging solutions.|
AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems (PDF)
|Using SignalTap to monitor signals located inside a system module generated by the Platform Designer.|
|AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer (PDF)||This application note examines the use of the Nios® II plug-in within the Signal Tap logic analyzer and presents the capabilities, configuration options, and use-modes for the plug-in.|
|AN 799: Quick Debugging of Intel® Arria® 10 Designs Using Signal Probe and Rapid Recompile||Access internal signals with minimal impact on your design.|
Block-Based Design Flows
The Intel® Quartus® Prime Pro Edition design software offers block-based design flows. There are of two types- the Incremental Block-Based Compilation and Design Block Reuse flows, which allow your geographically diverse development team to collaborate on a design.
Incremental Block-Based Compilation is preserving or emptying a partition within a project. This works with core partitions and requires no additional files or floor planning. The partition can be emptied, preserved at Source, Synthesis, and Final snapshots.
The Design Block Reuse flow enables you to reuse a block of a design in a different project by creating, preserving, and exporting a partition. With this feature, you can expect a clean hand off timing-closed modules between different teams.
Block-Based Design Resources
- Block-Based Design Flow section in the Intel® Quartus® Prime Pro Edition User Guide
- Tutorial: Intel® FPGA Design Block Reuse Flow (Intel® Arria® 10 GX, Intel® Quartus® Prime software v17.1) ›
- Design File (.zip) ›
- Training: Design Block Reuse (OBBDR100) ›
- Training: Incremental Block-Based Compilation (Part 1 of 3) (OIBBC100) ›
- Training: Incremental Block-Based Compilation (Part 2 of 3) (OIBBC101) ›
- Training: Incremental Block-Based Compilation (Part 3 of 3) (OIBBC102) ›
Rapid Recompile allows the reuse of previous synthesis and fitter results when possible, and does not reprocess unchanged design blocks. Rapid Recompile can reduce total compilation time after making small design changes. Rapid Recompile supports HDL-based functional ECO changes and enables you to reduce your compile time while preserving the performance of unchanged logic.
Rapid Recompile - Support Resources
|Running Rapid Recompile||Rapid Recompile section in volume 2 of the Intel® Quartus® Prime Pro Edition Handbook|
|AN 799: Quick Intel® Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile (PDF)||An application note showing how Rapid Recompile reduces the compile time for small changes|
Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function.
You can create multiple personas for a region of your device, and reconfigure that region without impacting operations in areas outside that persona.
For more information on Partial Reconfiguration, see the Partial Reconfiguration page.
The Intel® Quartus® Prime and Quartus® II software includes comprehensive scripting support for command-line and tool command language (Tcl) script design flows. Separate executables for each stage of the software design flow, such as synthesis, fitting, and timing analysis, include options for making common settings and performing common tasks. The Tcl scripting application programming interface (API) includes commands covering basic to advanced functionality.
You can use Intel® Quartus® Prime or Quartus® II software command-line executables in batch files, shell scripts, makefiles, and other scripts. For instance, use the following command to compile an existing project:
$ quartus_sh --flow compile
Use the Tcl API for any of the following tasks:
- Creating and managing projects
- Making assignments
- Compiling designs
- Extracting report data
- Performing timing analysis
You can get started with some of the examples in the Quartus® II software Tcl examples web page. Several other resources are listed below.
|Quartus® II Scripting Reference Manual||Covers both Quartus® software command-line executables and Tcl packages and commands from within a Quartus® software shell|
|Quartus® Prime Standard Edition Settings File Reference Manual||Covers parameter settings found in the Quartus® software Settings File (.qsf).|
|Command Line Scripting||A section of the Intel Quartus Prime Standard Edition User Guide.|
|Quartus® II Tcl Examples||A web page with several useful Tcl script examples.|
|Command Line Scripting (ODSW1197)||Online training presenting the command line scripting capabilities in the Intel® Quartus® software (30 min).|
|Introduction to Tcl (ODSW1180)||An Introduction to the Tcl scripting syntax.|
|Quartus® II Software Tcl Scripting (ODSW1190)||Tcl Scripting capabilities in the Quartus® II software.|
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