I/O Management and Board Development Support Center

AN775: I/O Timing Information Generation Guidelines

I/O timing information is crucial for early analysis during PCB board design stages. Generate timing parameters to help you adjust the timing budget of your design, considering I/O standards and pin placement.

This chapter of the Quartus Prime Pro Edition and Quartus Prime Standard Edition Handbook discusses FPGA I/O planning flow, detailing how and when to use the many I/O planning tools such as pin planner. It describes how to create top-level HDL files using pin planner's early I/O planning flow with custom megafunctions. It describes the methodology for I/O assignments and analysis, and discusses advanced I/O timing analysis with board trace models in Quartus Prime Pro Edition and Quartus Prime Standard Edition software.

This chapter of the Quartus Prime Standard Edition Handbook explains how to use the SSN analyzer and optimization tool in Quartus Prime Standard Edition software 9.0 and later. It discusses the tool flow and explains what is required to perform an accurate SSN analysis in your FPGA design. It also describes Quartus Prime Standard Edition software SSN optimization techniques and settings.

Using the Quartus® Prime Standard Edition Software: An Introduction

In this introductory training, you will become familiar with the basics of the easy-to-use Quartus® Prime Standard Edition software design environment. You will learn about the steps involved in the basic FPGA design flow and how to use the software in the flow, going from design entry to device programming all within one tool. Project creation and management, design and I/O assignments, and simulation are also covered.

• 80 Minute on-demand training course

Describes support for optional third-party PCB design tools by Siemens EDA and Cadence*. Also includes information about signal integrity analysis and simulations with HSPICE and IBIS Models.

The Mentor Graphics* I/O Designer software allows you to take advantage of the full FPGA symbol design, creation, editing, and back-annotation flow supported by the Mentor Graphics* tools.

This chapter describes efficient planning and assignment of I/O pins in your target device. Consider I/O standards, pin placement rules, and your PCB characteristics early in the design phase.

This document contains a step-by-step tutorial and checklist of best-practice guidelines to design and review a power distribution network (PDN).

Includes information and suggestions for designing and laying out high-speed boards with FPGAs.

Provides general information on high-speed board design.

Power Distribution Network (PDN) Tool

The easy-to-use power distribution network (PDN) design tool is a graphical tool used with all FPGAs to optimize the board-level PDN. The purpose of the board-level PDN is to distribute power and return currents from the voltage regulating module (VRM) to the FPGA power supplies, and support optimal transceiver signal integrity and FPGA performance.

With the ever-increasing operating speed of interfaces in traditional FPGA design, the timing and signal integrity margins between the FPGA and other devices on the board must be within specification and tolerance before building a PCB.

The Quartus® Prime software can export two different types of I/O models that are useful for different simulation situations, IBIS models and HSPICE models.