Quartus® Prime Design Software
The intuitive high-performance design environment. From design entry and synthesis to optimization, verification, and simulation, Quartus® Prime Design Software unlocks increased capabilities on devices with multi-million logic elements, providing designers with the ideal platform to meet next-generation design opportunities.
Everything You Need to Design for Altera® FPGAs, SoCs, and CPLDs
Watch how you can design with Quartus Prime Design Software.
What's New in Version 25.1
Agilex Device Support
- Added support for Agilex™ 3 FPGA C-Series.
- Additional support for Agilex™ 5 FPGA devices.
- Additional device support for Agilex™ 7 FPGAs F, I, and M-Series.
Enhancements
- Performance Boost in Nios V/g core.
- 8% Area Reduction with Nios V/c core.
- Ashling RiscFree VS Code Extension – Develop with Nios® V in VS Code.
- TinyML Example Design – Add machine learning to FPGA designs.
- Linux Reference Designs – Standard and regular editions for Linux development.
- Xen Hypervisor Support – Run virtualized FPGA applications.
- RTOS Support – Zephyr and Bare Metal are now supported; FreeRTOS coming soon.
- Installer Improvements – Faster, more flexible setup with parallel installation and dynamic component selection to reduce setup time and optimize disk space.
- Streaming Debug – High-speed hardware debugging with efficient real-time data transfer, configurable via Signal Tap (STP).
- Quartus Prime Pro 25.1 – Introduces native Altera AXI4 Bus Functional Models (BFMs) for improved simulation performance and easy integration, enabling a seamless transition with minimal changes.
- Improved Transceiver Protocol IP Simulation – Enhanced support for protocols like PCIe, Ethernet, Serial Lite, and JESD, with beta models for Ethernet and PCIe in 25.1 and up to 50% faster simulation and verification.
Other Features and Improvements
- Containerized Images for Quartus Prime Design Suite (QPDS): Available from Docker Hub for easier deployment and cloud compatibility.
- Static Timing Analysis Improvements – Smarter design closure with clearer failure categorization, a new summary separating timing and Design Assistant results, support for relative SDC file paths to improve portability, and fine-grain MTBF controls via toggle rate tuning.
- RAM Inference Improvements – Enhanced synthesis support including automatic inference of simple quad-port RAM and full support for byte-enable configurations (5, 8, 9, and 10 bits), enabling precise control to write individual bytes within a word.
- Enhanced the node-finder search filters to include various interface types for faster search queries.
What's New in FPGA AI Suite Version 25.1
Device and Development Platform Support:
- Agilex™ 3 Beta Support
- Generate Inference IP from FPGA AI Suite using Agilex™ 5 as the target device in the arch config file.
- Example design support on Agilex™ 5 FPGA E-Series 065B Modular Development Kit.
- SOC example design with ARM as host.
- Hostless JTAG-attach example design.
- Support limited to 2 years of Quartus Prime Pro releases.
FPGA AI Suite Features and Improvements
- New layout transform integrated with AI inference IP – supports folding and run-time configurability.
- Performance estimator takes user’s input of available external memory bandwidth.
- Previously performance estimator assumed memory bandwidth which could not be adjusted by the user.
- Useful for users designing for smaller devices like Agilex 5/3 which could have limited memory bandwidth.
- FPGA AI Suite 25.1 moves to OpenVINO 2024.6.
AI Models, Tooling, and Branding Updates
- YoloV7 model support.
- Identifies and locates objects within an image or video with high accuracy and speed. Used in Industrial quality control, surveillance, robotics etc.
- Altera Rebranding.
- RPM and DEB packages are now “altera-fpga-ai-suite-<version>”.
- AI Suite now installs into ‘/opt/altera’ instead of ‘/opt/intel’.
What's New for FPGA IP in Version 25.1
Introducing Agilex™ 3 IPs
- Flexible I/O support with high-voltage, high-speed interfaces - MIPI D-PHY, 1.25 Gbps LVDS.
- Robust data-transfer capabilities - 12.5Gbps transceivers, PCIe 3.0, and 10GE + 1GE low-latency MAC hard IPs.
- Manage data transfers between non-contiguous memory locations without CPU overhead using sSGDMA IP.
- High-speed, low-latency data transfer for varied applications using SerialLite IV.
- Precise timing synchronization across network devices with TSE–1588 support.
- Cost-effective memory support with LPDDR4 up to 2133Mbps.
- Seamless integration with ARM Cortex processors using HPS EMIF.
- Robust synchronization features for multiple data converters using 12.5Gbps JESD204B.
- Comprehensive debugging and testing of transceiver links using the Transceiver Toolkit.
- High-resolution image and video processing using Video and Vision Processing (VVP) IP suite.
Agilex™ 5 IP Updates
- Introducing LTPI: The next-gen protocol for DC-SCM 2.0, offering higher bandwidth and scalability for seamless low-speed signal tunneling.
- Real-time adjustments of multiple configurations using Dynamic Reconfiguration - PMA-D.
- Multi-Channel Direct Memory Access (MCDMA) for PCIe 3.0/4.0 x2/x4 supporting both RP and EP.
- Deterministic low-latency communication with Ethernet TSN @ 10M/100M/1/2.5 G + SGMI.
- Interlaken @ 12.5Gbps per serial lane introduced in Agilex 5 D Series.
- JESD204B up to 17.16Gbps with UTK support.
- JESD204C protocol included in Dual-Simplex mode.
Additional Resources
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Frequently Asked Questions About Quartus® Prime Design Software
Quartus® Prime Software enables a fast path to turning Altera® FPGA, SoC, and CPLD designs into reality. It provides tools and features needed to help with every step from design entry and synthesis to optimization, verification, and simulation. Check out the Quartus Prime Software brochure for more details.
Quartus® Prime Pro Edition Software and Standard Edition Software require a paid license, but the Lite Edition is license-free. A fixed-node subscription supports access to the Pro Edition and Standard Edition, as well as the Questa*-Altera® FPGA Edition, with one year of maintenance. To obtain a license, go to our FPGA Licensing Support Center.
If you are ready to purchase a license or need advanced FPGA and SoC features—such as support for Agilex™, Stratix® 10, Arria® 10, and Cyclone® 10 LP device families—first purchase a paid license from our FPGA Licensing Support Center.
To get started with the free version of Quartus® Prime Lite Edition Software or to download a licensed version, go to Quartus Prime Software downloads.