Intel® Quartus® Prime Standard Edition User Guide: Design Constraints
ID
683492
Date
1/10/2019
Public
2.1. I/O Planning Overview
2.2. Assigning I/O Pins
2.3. Importing and Exporting I/O Pin Assignments
2.4. Validating Pin Assignments
2.5. Verifying I/O Timing
2.6. Viewing Routing and Timing Delays
2.7. Analyzing Simultaneous Switching Noise
2.8. Scripting API
2.9. Managing Device I/O Pins Revision History
2. Managing Device I/O Pins
This chapter describes efficient planning and assignment of I/O pins in your target device. Consider I/O standards, pin placement rules, and your PCB characteristics early in the design phase.
Figure 4. Pin Planner GUI
I/O Planning Task |
Click to Access |
---|---|
Edit, validate, or export pin assignments |
Assignments > Pin Planner |
View tailored pin planning advice |
Tools > Advisors > Pin Advisor |
Validate pin assignments against design rules |
Processing > Start > Start I/O Assignment Analysis |
For more information about special pin assignment features for the Intel® Arria® 10 SoC devices, refer to Instantiating the HPS Component in the Intel® Arria® 10 Hard Processor System Technical Reference Manual.